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Re: [Qemu-devel] [PULL v4 0/7] riscv-pull queue
From: |
Alistair Francis |
Subject: |
Re: [Qemu-devel] [PULL v4 0/7] riscv-pull queue |
Date: |
Mon, 9 Jul 2018 14:52:31 -0700 |
On Mon, Jul 9, 2018 at 3:00 AM, Andreas Schwab <address@hidden> wrote:
> What is the state of the sifive_u emulation? When I tried to boot a bbl
> with an included kernel I get these errors:
>
> qemu-system-riscv64: plic: invalid register write: 00002090
> qemu-system-riscv64: plic: invalid register write: 00002094
> qemu-system-riscv64: plic: invalid register write: 00002098
> qemu-system-riscv64: plic: invalid register write: 0000209c
> qemu-system-riscv64: plic: invalid register write: 000020a0
> qemu-system-riscv64: plic: invalid register write: 000020a4
> qemu-system-riscv64: plic: invalid register write: 000020a8
> qemu-system-riscv64: plic: invalid register write: 000020ac
> qemu-system-riscv64: plic: invalid register write: 000020b0
> qemu-system-riscv64: plic: invalid register write: 000020b4
I see those as well. I haven't investigated but I assume we are just
not completely modelling the PLIC. In saying that it should still
boot. Do you not see the kernel booting?
Alistair
>
> Andreas.
>
> --
> Andreas Schwab, SUSE Labs, address@hidden
> GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE 1748 E4D4 88E3 0EEA B9D7
> "And now for something completely different."
- [Qemu-devel] [PULL v4 0/7] riscv-pull queue, Alistair Francis, 2018/07/05
- [Qemu-devel] [PULL v4 5/7] hw/riscv/sifive_u: Set the interrupt controller number of interrupts, Alistair Francis, 2018/07/05
- [Qemu-devel] [PULL v4 3/7] hw/riscv/sifive_plic: Use gpios instead of irqs, Alistair Francis, 2018/07/05
- [Qemu-devel] [PULL v4 7/7] hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device, Alistair Francis, 2018/07/05
- [Qemu-devel] [PULL v4 2/7] hw/riscv/sifive_e: Create a SiFive E SoC object, Alistair Francis, 2018/07/05
- [Qemu-devel] [PULL v4 6/7] hw/riscv/sifive_u: Move the uart device tree node under /soc/, Alistair Francis, 2018/07/05
- [Qemu-devel] [PULL v4 1/7] hw/riscv/sifive_u: Create a SiFive U SoC object, Alistair Francis, 2018/07/05
- [Qemu-devel] [PULL v4 4/7] hw/riscv/sifive_u: Set the soc device tree node as a simple-bus, Alistair Francis, 2018/07/05
- Re: [Qemu-devel] [PULL v4 0/7] riscv-pull queue, Peter Maydell, 2018/07/06
- Re: [Qemu-devel] [PULL v4 0/7] riscv-pull queue, Andreas Schwab, 2018/07/09
- Re: [Qemu-devel] [PULL v4 0/7] riscv-pull queue,
Alistair Francis <=