[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v3 24/38] target-microblaze: mmu: Add R_TBLX_MISS ma
From: |
Edgar E. Iglesias |
Subject: |
[Qemu-devel] [PATCH v3 24/38] target-microblaze: mmu: Add R_TBLX_MISS macros |
Date: |
Wed, 16 May 2018 20:51:32 +0200 |
From: "Edgar E. Iglesias" <address@hidden>
Add a R_TBLX_MISS MASK and SHIFT macros.
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
target/microblaze/mmu.c | 5 +++--
target/microblaze/mmu.h | 4 ++++
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c
index 0019ebd18f..f4a4c339c9 100644
--- a/target/microblaze/mmu.c
+++ b/target/microblaze/mmu.c
@@ -292,8 +292,9 @@ void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
v & TLB_EPN_MASK, 0, cpu_mmu_index(env,
false));
if (hit) {
env->mmu.regs[MMU_R_TLBX] = lu.idx;
- } else
- env->mmu.regs[MMU_R_TLBX] |= 0x80000000;
+ } else {
+ env->mmu.regs[MMU_R_TLBX] |= R_TBLX_MISS_MASK;
+ }
break;
}
default:
diff --git a/target/microblaze/mmu.h b/target/microblaze/mmu.h
index 3b7a9983d5..113539c6e9 100644
--- a/target/microblaze/mmu.h
+++ b/target/microblaze/mmu.h
@@ -54,6 +54,10 @@
#define TLB_M 0x00000002 /* Memory is coherent */
#define TLB_G 0x00000001 /* Memory is guarded from prefetch */
+/* TLBX */
+#define R_TBLX_MISS_SHIFT 31
+#define R_TBLX_MISS_MASK (1U << R_TBLX_MISS_SHIFT)
+
#define TLB_ENTRIES 64
struct microblaze_mmu
--
2.14.1
- [Qemu-devel] [PATCH v3 15/38] target-microblaze: Break out trap_userspace(), (continued)
- [Qemu-devel] [PATCH v3 15/38] target-microblaze: Break out trap_userspace(), Edgar E. Iglesias, 2018/05/16
- [Qemu-devel] [PATCH v3 16/38] target-microblaze: Break out trap_illegal(), Edgar E. Iglesias, 2018/05/16
- [Qemu-devel] [PATCH v3 18/38] target-microblaze: dec_msr: Reuse more code when reg-decoding, Edgar E. Iglesias, 2018/05/16
- [Qemu-devel] [PATCH v3 19/38] target-microblaze: dec_msr: Fix MTS to FSR, Edgar E. Iglesias, 2018/05/16
- [Qemu-devel] [PATCH v3 17/38] target-microblaze: dec_msr: Use bool and extract32, Edgar E. Iglesias, 2018/05/16
- [Qemu-devel] [PATCH v3 20/38] target-microblaze: Make special registers 64-bit, Edgar E. Iglesias, 2018/05/16
- [Qemu-devel] [PATCH v3 23/38] target-microblaze: Implement MFSE EAR, Edgar E. Iglesias, 2018/05/16
- [Qemu-devel] [PATCH v3 21/38] target-microblaze: Setup for 64bit addressing, Edgar E. Iglesias, 2018/05/16
- [Qemu-devel] [PATCH v3 24/38] target-microblaze: mmu: Add R_TBLX_MISS macros,
Edgar E. Iglesias <=
- [Qemu-devel] [PATCH v3 25/38] target-microblaze: mmu: Remove unused register state, Edgar E. Iglesias, 2018/05/16
- [Qemu-devel] [PATCH v3 26/38] target-microblaze: mmu: Prepare for 64-bit addresses, Edgar E. Iglesias, 2018/05/16
- [Qemu-devel] [PATCH v3 27/38] target-microblaze: mmu: Add a configurable output address mask, Edgar E. Iglesias, 2018/05/16
- [Qemu-devel] [PATCH v3 28/38] target-microblaze: dec_msr: Plug a temp leak, Edgar E. Iglesias, 2018/05/16
- [Qemu-devel] [PATCH v3 30/38] target-microblaze: Allow address sizes between 32 and 64 bits, Edgar E. Iglesias, 2018/05/16
- [Qemu-devel] [PATCH v3 32/38] target-microblaze: mmu: Cleanup debug log messages, Edgar E. Iglesias, 2018/05/16
- [Qemu-devel] [PATCH v3 33/38] target-microblaze: Use table based condition-codes conversion, Edgar E. Iglesias, 2018/05/16