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Re: [Qemu-devel] [PATCH v8 23/35] RISC-V: Simplify riscv_cpu_local_irqs_
From: |
Alistair Francis |
Subject: |
Re: [Qemu-devel] [PATCH v8 23/35] RISC-V: Simplify riscv_cpu_local_irqs_pending |
Date: |
Fri, 27 Apr 2018 22:33:31 +0000 |
On Wed, Apr 25, 2018 at 4:56 PM Michael Clark <address@hidden> wrote:
> This commit is intended to improve readability.
> There is no change to the logic.
> Cc: Sagar Karandikar <address@hidden>
> Cc: Bastian Koppelmann <address@hidden>
> Cc: Palmer Dabbelt <address@hidden>
> Cc: Alistair Francis <address@hidden>
> Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Alistair
> ---
> target/riscv/helper.c | 34 ++++++++++++----------------------
> 1 file changed, 12 insertions(+), 22 deletions(-)
> diff --git a/target/riscv/helper.c b/target/riscv/helper.c
> index 3b57e13..47d116e 100644
> --- a/target/riscv/helper.c
> +++ b/target/riscv/helper.c
> @@ -35,28 +35,18 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool
ifetch)
> }
> #ifndef CONFIG_USER_ONLY
> -/*
> - * Return RISC-V IRQ number if an interrupt should be taken, else -1.
> - * Used in cpu-exec.c
> - *
> - * Adapted from Spike's processor_t::take_interrupt()
> - */
> -static int riscv_cpu_hw_interrupts_pending(CPURISCVState *env)
> +static int riscv_cpu_local_irq_pending(CPURISCVState *env)
> {
> - target_ulong pending_interrupts = atomic_read(&env->mip) & env->mie;
> -
> - target_ulong mie = get_field(env->mstatus, MSTATUS_MIE);
> - target_ulong m_enabled = env->priv < PRV_M || (env->priv == PRV_M &&
mie);
> - target_ulong enabled_interrupts = pending_interrupts &
> - ~env->mideleg & -m_enabled;
> -
> - target_ulong sie = get_field(env->mstatus, MSTATUS_SIE);
> - target_ulong s_enabled = env->priv < PRV_S || (env->priv == PRV_S &&
sie);
> - enabled_interrupts |= pending_interrupts & env->mideleg &
> - -s_enabled;
> -
> - if (enabled_interrupts) {
> - return ctz64(enabled_interrupts); /* since non-zero */
> + target_ulong mstatus_mie = get_field(env->mstatus, MSTATUS_MIE);
> + target_ulong mstatus_sie = get_field(env->mstatus, MSTATUS_SIE);
> + target_ulong pending = atomic_read(&env->mip) & env->mie;
> + target_ulong mie = env->priv < PRV_M || (env->priv == PRV_M &&
mstatus_mie);
> + target_ulong sie = env->priv < PRV_S || (env->priv == PRV_S &&
mstatus_sie);
> + target_ulong irqs = (pending & ~env->mideleg & -mie) |
> + (pending & env->mideleg & -sie);
> +
> + if (irqs) {
> + return ctz64(irqs); /* since non-zero */
> } else {
> return EXCP_NONE; /* indicates no pending interrupt */
> }
> @@ -69,7 +59,7 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int
interrupt_request)
> if (interrupt_request & CPU_INTERRUPT_HARD) {
> RISCVCPU *cpu = RISCV_CPU(cs);
> CPURISCVState *env = &cpu->env;
> - int interruptno = riscv_cpu_hw_interrupts_pending(env);
> + int interruptno = riscv_cpu_local_irq_pending(env);
> if (interruptno >= 0) {
> cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno;
> riscv_cpu_do_interrupt(cs);
> --
> 2.7.0
- Re: [Qemu-devel] [PATCH v8 18/35] RISC-V: Clear mtval/stval on exceptions without info, (continued)
- [Qemu-devel] [PATCH v8 19/35] RISC-V: Allow S-mode mxr access when priv ISA >= v1.10, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 20/35] RISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 21/35] RISC-V: Add mcycle/minstret support for -icount auto, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 22/35] RISC-V: Use atomic_cmpxchg to update PLIC bitmaps, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 23/35] RISC-V: Simplify riscv_cpu_local_irqs_pending, Michael Clark, 2018/04/25
- Re: [Qemu-devel] [PATCH v8 23/35] RISC-V: Simplify riscv_cpu_local_irqs_pending,
Alistair Francis <=
- [Qemu-devel] [PATCH v8 24/35] RISC-V: Allow setting and clearing multiple irqs, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 25/35] RISC-V: Move non-ops from op_helper to cpu_helper, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 26/35] RISC-V: Update CSR and interrupt definitions, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 28/35] RISC-V: Implement atomic mip/sip CSR updates, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 27/35] RISC-V: Implement modular CSR helper interface, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 29/35] RISC-V: Implement existential predicates for CSRs, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 30/35] RISC-V: Split out mstatus_fs from tb_flags, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 31/35] RISC-V: Mark mstatus.fs dirty, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 32/35] RISC-V: Implement mstatus.TSR/TW/TVM, Michael Clark, 2018/04/25