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[Qemu-devel] [PATCH v8 20/35] RISC-V: Use [ms]counteren CSRs when priv I
From: |
Michael Clark |
Subject: |
[Qemu-devel] [PATCH v8 20/35] RISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10 |
Date: |
Thu, 26 Apr 2018 11:45:23 +1200 |
Privileged ISA v1.9.1 defines mscounteren and mucounteren:
* mscounteren contains a mask of counters available to S-mode
* mucounteren contains a mask of counters available to U-mode
Privileged ISA v1.10 defines mcounteren and scounteren:
* mcounteren contains a mask of counters available to S-mode
* scounteren contains a mask of counters available to U-mode
mcounteren and scounteren CSR registers were implemented
however they were not honoured for counter accesses when
the privilege ISA was >= v1.10. This fix solves the issue
by coalescing the counter enable registers. In addition
the code now generates illegal instruction exceptions
for accesses to the counter enabled registers depending
on the privileged ISA version.
- Coalesce mscounteren and mcounteren into one variable
- Coalesce mucounteren and scounteren into one variable
- Makes mcounteren and scounteren CSR accesses generate
illegal instructions when the privileged ISA <= v1.9.1
- Makes mscounteren and mucounteren CSR accesses generate
illegal instructions when the privileged ISA >= v1.10
Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Cc: Palmer Dabbelt <address@hidden>
Cc: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
---
target/riscv/cpu.h | 6 ++---
target/riscv/op_helper.c | 63 +++++++++++++++++++++++++++++++++++++-----------
2 files changed, 51 insertions(+), 18 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 890cd96..e0608e6 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -151,10 +151,8 @@ struct CPURISCVState {
target_ulong mcause;
target_ulong mtval; /* since: priv-1.10.0 */
- uint32_t mucounteren;
- uint32_t mscounteren;
- target_ulong scounteren; /* since: priv-1.10.0 */
- target_ulong mcounteren; /* since: priv-1.10.0 */
+ target_ulong scounteren;
+ target_ulong mcounteren;
target_ulong sscratch;
target_ulong mscratch;
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 88c263a..2daf07c 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -227,11 +227,19 @@ void csr_write_helper(CPURISCVState *env, target_ulong
val_to_write,
break;
#endif
case CSR_MUCOUNTEREN:
- env->mucounteren = val_to_write;
- break;
+ if (env->priv_ver <= PRIV_VERSION_1_09_1) {
+ env->scounteren = val_to_write;
+ break;
+ } else {
+ goto do_illegal;
+ }
case CSR_MSCOUNTEREN:
- env->mscounteren = val_to_write;
- break;
+ if (env->priv_ver <= PRIV_VERSION_1_09_1) {
+ env->mcounteren = val_to_write;
+ break;
+ } else {
+ goto do_illegal;
+ }
case CSR_SSTATUS: {
target_ulong ms = env->mstatus;
target_ulong mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_UIE
@@ -287,8 +295,12 @@ void csr_write_helper(CPURISCVState *env, target_ulong
val_to_write,
}
break;
case CSR_SCOUNTEREN:
- env->scounteren = val_to_write;
- break;
+ if (env->priv_ver >= PRIV_VERSION_1_10_0) {
+ env->scounteren = val_to_write;
+ break;
+ } else {
+ goto do_illegal;
+ }
case CSR_SSCRATCH:
env->sscratch = val_to_write;
break;
@@ -308,8 +320,12 @@ void csr_write_helper(CPURISCVState *env, target_ulong
val_to_write,
}
break;
case CSR_MCOUNTEREN:
- env->mcounteren = val_to_write;
- break;
+ if (env->priv_ver >= PRIV_VERSION_1_10_0) {
+ env->mcounteren = val_to_write;
+ break;
+ } else {
+ goto do_illegal;
+ }
case CSR_MSCRATCH:
env->mscratch = val_to_write;
break;
@@ -347,6 +363,9 @@ void csr_write_helper(CPURISCVState *env, target_ulong
val_to_write,
pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val_to_write);
break;
#endif
+#if !defined(CONFIG_USER_ONLY)
+ do_illegal:
+#endif
default:
do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
@@ -360,8 +379,8 @@ void csr_write_helper(CPURISCVState *env, target_ulong
val_to_write,
target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno)
{
#ifndef CONFIG_USER_ONLY
- target_ulong ctr_en = env->priv == PRV_U ? env->mucounteren :
- env->priv == PRV_S ? env->mscounteren : -1U;
+ target_ulong ctr_en = env->priv == PRV_U ? env->scounteren :
+ env->priv == PRV_S ? env->mcounteren : -1U;
#else
target_ulong ctr_en = -1;
#endif
@@ -436,9 +455,17 @@ target_ulong csr_read_helper(CPURISCVState *env,
target_ulong csrno)
#endif
break;
case CSR_MUCOUNTEREN:
- return env->mucounteren;
+ if (env->priv_ver <= PRIV_VERSION_1_09_1) {
+ return env->scounteren;
+ } else {
+ break; /* illegal instruction */
+ }
case CSR_MSCOUNTEREN:
- return env->mscounteren;
+ if (env->priv_ver <= PRIV_VERSION_1_09_1) {
+ return env->mcounteren;
+ } else {
+ break; /* illegal instruction */
+ }
case CSR_SSTATUS: {
target_ulong mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_UIE
| SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS
@@ -463,7 +490,11 @@ target_ulong csr_read_helper(CPURISCVState *env,
target_ulong csrno)
case CSR_STVEC:
return env->stvec;
case CSR_SCOUNTEREN:
- return env->scounteren;
+ if (env->priv_ver >= PRIV_VERSION_1_10_0) {
+ return env->scounteren;
+ } else {
+ break; /* illegal instruction */
+ }
case CSR_SCAUSE:
return env->scause;
case CSR_SATP: /* CSR_SPTBR */
@@ -508,7 +539,11 @@ target_ulong csr_read_helper(CPURISCVState *env,
target_ulong csrno)
case CSR_MTVEC:
return env->mtvec;
case CSR_MCOUNTEREN:
- return env->mcounteren;
+ if (env->priv_ver >= PRIV_VERSION_1_10_0) {
+ return env->mcounteren;
+ } else {
+ break; /* illegal instruction */
+ }
case CSR_MEDELEG:
return env->medeleg;
case CSR_MIDELEG:
--
2.7.0
- Re: [Qemu-devel] [PATCH v8 14/35] RISC-V: Update E order and I extension order, (continued)
- [Qemu-devel] [PATCH v8 15/35] RISC-V: Hardwire satp to 0 for no-mmu case, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 16/35] RISC-V: Make mtvec/stvec ignore vectored traps, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 17/35] RISC-V: No traps on writes to misa, minstret, mcycle, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 18/35] RISC-V: Clear mtval/stval on exceptions without info, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 19/35] RISC-V: Allow S-mode mxr access when priv ISA >= v1.10, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 20/35] RISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10,
Michael Clark <=
- [Qemu-devel] [PATCH v8 21/35] RISC-V: Add mcycle/minstret support for -icount auto, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 22/35] RISC-V: Use atomic_cmpxchg to update PLIC bitmaps, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 23/35] RISC-V: Simplify riscv_cpu_local_irqs_pending, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 24/35] RISC-V: Allow setting and clearing multiple irqs, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 25/35] RISC-V: Move non-ops from op_helper to cpu_helper, Michael Clark, 2018/04/25