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[Qemu-devel] [PULL 35/42] arm/translate-a64: add FP16 FRSQRTE to simd_tw
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 35/42] arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16 |
Date: |
Thu, 1 Mar 2018 11:23:56 +0000 |
From: Alex Bennée <address@hidden>
Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/translate-a64.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 1096ff48ac..86231b33bb 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -11388,6 +11388,7 @@ static void disas_simd_two_reg_misc_fp16(DisasContext
*s, uint32_t insn)
case 0x6f: /* FNEG */
need_fpst = false;
break;
+ case 0x7d: /* FRSQRTE */
case 0x7f: /* FSQRT (vector) */
break;
default:
@@ -11452,6 +11453,9 @@ static void disas_simd_two_reg_misc_fp16(DisasContext
*s, uint32_t insn)
case 0x6f: /* FNEG */
tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
break;
+ case 0x7d: /* FRSQRTE */
+ gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus);
+ break;
default:
g_assert_not_reached();
}
@@ -11504,6 +11508,9 @@ static void disas_simd_two_reg_misc_fp16(DisasContext
*s, uint32_t insn)
case 0x6f: /* FNEG */
tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
break;
+ case 0x7d: /* FRSQRTE */
+ gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus);
+ break;
case 0x7f: /* FSQRT */
gen_helper_sqrt_f16(tcg_res, tcg_op, tcg_fpstatus);
break;
--
2.16.2
- [Qemu-devel] [PULL 21/42] arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16, (continued)
- [Qemu-devel] [PULL 21/42] arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 24/42] arm/translate-a64: initial decode for simd_two_reg_misc_fp16, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 22/42] arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 25/42] arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 26/42] arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 27/42] arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 31/42] arm/translate-a64: add FP16 FRECPE, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 28/42] arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 40/42] target/arm: Enable ARM_V8_FP16 feature bit for the AArch64 "any" CPU, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 30/42] arm/helper.c: re-factor recpe and add recepe_f16, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 35/42] arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16,
Peter Maydell <=
- [Qemu-devel] [PULL 19/42] arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 11/42] target/arm/cpu.h: update comment for half-precision values, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 23/42] arm/translate-a64: add FP16 x2 ops for simd_indexed, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 01/42] hw: register: Run post_write hook on reset, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 29/42] arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 32/42] arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 33/42] arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 36/42] arm/translate-a64: add FP16 FMOV to simd_mod_imm, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 34/42] arm/helper.c: re-factor rsqrte and add rsqrte_f16, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 38/42] arm/translate-a64: implement simd_scalar_three_reg_same_fp16, Peter Maydell, 2018/03/01