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[Qemu-devel] [PULL 31/42] arm/translate-a64: add FP16 FRECPE
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 31/42] arm/translate-a64: add FP16 FRECPE |
Date: |
Thu, 1 Mar 2018 11:23:52 +0000 |
From: Alex Bennée <address@hidden>
Now we have added f16 during the re-factoring we can simply call the
helper.
Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/translate-a64.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 9f2c3682dc..50b4fa4ce4 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -11311,6 +11311,8 @@ static void disas_simd_two_reg_misc_fp16(DisasContext
*s, uint32_t insn)
case 0x6d: /* FCMLE (zero) */
handle_2misc_fcmp_zero(s, fpop, is_scalar, 0, is_q, MO_16, rn, rd);
return;
+ case 0x3d: /* FRECPE */
+ break;
case 0x18: /* FRINTN */
need_rmode = true;
only_in_vector = true;
@@ -11431,6 +11433,9 @@ static void disas_simd_two_reg_misc_fp16(DisasContext
*s, uint32_t insn)
case 0x3b: /* FCVTZS */
gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus);
break;
+ case 0x3d: /* FRECPE */
+ gen_helper_recpe_f16(tcg_res, tcg_op, tcg_fpstatus);
+ break;
case 0x5a: /* FCVTNU */
case 0x5b: /* FCVTMU */
case 0x5c: /* FCVTAU */
@@ -11466,6 +11471,9 @@ static void disas_simd_two_reg_misc_fp16(DisasContext
*s, uint32_t insn)
case 0x3b: /* FCVTZS */
gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus);
break;
+ case 0x3d: /* FRECPE */
+ gen_helper_recpe_f16(tcg_res, tcg_op, tcg_fpstatus);
+ break;
case 0x5a: /* FCVTNU */
case 0x5b: /* FCVTMU */
case 0x5c: /* FCVTAU */
--
2.16.2
- [Qemu-devel] [PULL 03/42] xilinx_spips: Use 8 dummy cycles with the QIOR/QIOR4 commands, (continued)
- [Qemu-devel] [PULL 03/42] xilinx_spips: Use 8 dummy cycles with the QIOR/QIOR4 commands, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 02/42] xilinx_spips: Enable only two slaves when reading/writing with stripe, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 17/42] arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 13/42] target/arm/helper: pass explicit fpst to set_rmode, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 21/42] arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 24/42] arm/translate-a64: initial decode for simd_two_reg_misc_fp16, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 22/42] arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 25/42] arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 26/42] arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 27/42] arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 31/42] arm/translate-a64: add FP16 FRECPE,
Peter Maydell <=
- [Qemu-devel] [PULL 28/42] arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 40/42] target/arm: Enable ARM_V8_FP16 feature bit for the AArch64 "any" CPU, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 30/42] arm/helper.c: re-factor recpe and add recepe_f16, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 35/42] arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 19/42] arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 11/42] target/arm/cpu.h: update comment for half-precision values, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 23/42] arm/translate-a64: add FP16 x2 ops for simd_indexed, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 01/42] hw: register: Run post_write hook on reset, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 29/42] arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 32/42] arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16, Peter Maydell, 2018/03/01