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[Qemu-devel] [PULL 26/26] hw/intc/arm_gic: reserved register addresses a
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 26/26] hw/intc/arm_gic: reserved register addresses are RAZ/WI |
Date: |
Thu, 11 Jan 2018 13:38:22 +0000 |
The GICv2 specification says that reserved register addresses
must RAZ/WI; now that we implement external abort handling
for Arm CPUs this means we must return MEMTX_OK rather than
MEMTX_ERROR, to avoid generating a spurious guest data abort.
Cc: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Reviewed-by: Alistair Francis <address@hidden>
---
hw/intc/arm_gic.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 5a0e2a3..d701e49 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -1261,7 +1261,8 @@ static MemTxResult gic_cpu_read(GICState *s, int cpu, int
offset,
default:
qemu_log_mask(LOG_GUEST_ERROR,
"gic_cpu_read: Bad offset %x\n", (int)offset);
- return MEMTX_ERROR;
+ *data = 0;
+ break;
}
return MEMTX_OK;
}
@@ -1329,7 +1330,7 @@ static MemTxResult gic_cpu_write(GICState *s, int cpu,
int offset,
default:
qemu_log_mask(LOG_GUEST_ERROR,
"gic_cpu_write: Bad offset %x\n", (int)offset);
- return MEMTX_ERROR;
+ return MEMTX_OK;
}
gic_update(s);
return MEMTX_OK;
--
2.7.4
- [Qemu-devel] [PULL 12/26] imx_fec: Change queue flushing heuristics, (continued)
- [Qemu-devel] [PULL 12/26] imx_fec: Change queue flushing heuristics, Peter Maydell, 2018/01/11
- [Qemu-devel] [PULL 19/26] imx_fec: Fix a typo in imx_enet_receive(), Peter Maydell, 2018/01/11
- [Qemu-devel] [PULL 15/26] imx_fec: Use MIN instead of explicit ternary operator, Peter Maydell, 2018/01/11
- [Qemu-devel] [PULL 14/26] imx_fec: Use ENET_FTRL to determine truncation length, Peter Maydell, 2018/01/11
- [Qemu-devel] [PULL 16/26] imx_fec: Emulate SHIFT16 in ENETx_RACC, Peter Maydell, 2018/01/11
- [Qemu-devel] [PULL 07/26] linux-user: Activate armeb handler registration, Peter Maydell, 2018/01/11
- [Qemu-devel] [PULL 06/26] linux-user: Separate binfmt arm CPU families, Peter Maydell, 2018/01/11
- [Qemu-devel] [PULL 21/26] hw/timer/pxa2xx_timer: replace hw_error() -> qemu_log_mask(), Peter Maydell, 2018/01/11
- [Qemu-devel] [PULL 24/26] target/arm: Make disas_thumb2_insn() generate its own UNDEF exceptions, Peter Maydell, 2018/01/11
- [Qemu-devel] [PULL 20/26] imx_fec: Reserve full FSL_IMX25_FEC_SIZE page for the register file, Peter Maydell, 2018/01/11
- [Qemu-devel] [PULL 26/26] hw/intc/arm_gic: reserved register addresses are RAZ/WI,
Peter Maydell <=
- [Qemu-devel] [PULL 25/26] hw/intc/arm_gicv3: Make reserved register addresses RAZ/WI, Peter Maydell, 2018/01/11
- [Qemu-devel] [PULL 17/26] imx_fec: Add support for multiple Tx DMA rings, Peter Maydell, 2018/01/11
- [Qemu-devel] [PULL 02/26] linux-user: Add separate aarch64_be uname, Peter Maydell, 2018/01/11
- [Qemu-devel] [PULL 23/26] linux-user/arm/nwfpe: Check coprocessor number for FPA emulation, Peter Maydell, 2018/01/11
- [Qemu-devel] [PULL 22/26] hw/sd/pxa2xx_mmci: add read/write() trace events, Peter Maydell, 2018/01/11
- Re: [Qemu-devel] [PULL 00/26] target-arm queue, no-reply, 2018/01/11
- Re: [Qemu-devel] [PULL 00/26] target-arm queue, Peter Maydell, 2018/01/11