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[Qemu-devel] [PULL 21/26] hw/timer/pxa2xx_timer: replace hw_error() -> q
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 21/26] hw/timer/pxa2xx_timer: replace hw_error() -> qemu_log_mask() |
Date: |
Thu, 11 Jan 2018 13:38:17 +0000 |
From: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/timer/pxa2xx_timer.c | 17 +++++++++++++++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/hw/timer/pxa2xx_timer.c b/hw/timer/pxa2xx_timer.c
index 68ba5a7..a489bf5 100644
--- a/hw/timer/pxa2xx_timer.c
+++ b/hw/timer/pxa2xx_timer.c
@@ -13,6 +13,7 @@
#include "sysemu/sysemu.h"
#include "hw/arm/pxa.h"
#include "hw/sysbus.h"
+#include "qemu/log.h"
#define OSMR0 0x00
#define OSMR1 0x04
@@ -252,8 +253,14 @@ static uint64_t pxa2xx_timer_read(void *opaque, hwaddr
offset,
case OSNR:
return s->snapshot;
default:
+ qemu_log_mask(LOG_UNIMP,
+ "%s: unknown register 0x%02" HWADDR_PRIx "\n",
+ __func__, offset);
+ break;
badreg:
- hw_error("pxa2xx_timer_read: Bad offset " REG_FMT "\n", offset);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: incorrect register 0x%02" HWADDR_PRIx "\n",
+ __func__, offset);
}
return 0;
@@ -377,8 +384,14 @@ static void pxa2xx_timer_write(void *opaque, hwaddr offset,
}
break;
default:
+ qemu_log_mask(LOG_UNIMP,
+ "%s: unknown register 0x%02" HWADDR_PRIx " "
+ "(value 0x%08" PRIx64 ")\n", __func__, offset, value);
+ break;
badreg:
- hw_error("pxa2xx_timer_write: Bad offset " REG_FMT "\n", offset);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: incorrect register 0x%02" HWADDR_PRIx " "
+ "(value 0x%08" PRIx64 ")\n", __func__, offset, value);
}
}
--
2.7.4
- [Qemu-devel] [PULL 18/26] imx_fec: Use correct length for packet size, (continued)
- [Qemu-devel] [PULL 18/26] imx_fec: Use correct length for packet size, Peter Maydell, 2018/01/11
- [Qemu-devel] [PULL 10/26] imx_fec: Do not link to netdev, Peter Maydell, 2018/01/11
- [Qemu-devel] [PULL 03/26] linux-user: Fix endianess of aarch64 signal trampoline, Peter Maydell, 2018/01/11
- [Qemu-devel] [PULL 12/26] imx_fec: Change queue flushing heuristics, Peter Maydell, 2018/01/11
- [Qemu-devel] [PULL 19/26] imx_fec: Fix a typo in imx_enet_receive(), Peter Maydell, 2018/01/11
- [Qemu-devel] [PULL 15/26] imx_fec: Use MIN instead of explicit ternary operator, Peter Maydell, 2018/01/11
- [Qemu-devel] [PULL 14/26] imx_fec: Use ENET_FTRL to determine truncation length, Peter Maydell, 2018/01/11
- [Qemu-devel] [PULL 16/26] imx_fec: Emulate SHIFT16 in ENETx_RACC, Peter Maydell, 2018/01/11
- [Qemu-devel] [PULL 07/26] linux-user: Activate armeb handler registration, Peter Maydell, 2018/01/11
- [Qemu-devel] [PULL 06/26] linux-user: Separate binfmt arm CPU families, Peter Maydell, 2018/01/11
- [Qemu-devel] [PULL 21/26] hw/timer/pxa2xx_timer: replace hw_error() -> qemu_log_mask(),
Peter Maydell <=
- [Qemu-devel] [PULL 24/26] target/arm: Make disas_thumb2_insn() generate its own UNDEF exceptions, Peter Maydell, 2018/01/11
- [Qemu-devel] [PULL 20/26] imx_fec: Reserve full FSL_IMX25_FEC_SIZE page for the register file, Peter Maydell, 2018/01/11
- [Qemu-devel] [PULL 26/26] hw/intc/arm_gic: reserved register addresses are RAZ/WI, Peter Maydell, 2018/01/11
- [Qemu-devel] [PULL 25/26] hw/intc/arm_gicv3: Make reserved register addresses RAZ/WI, Peter Maydell, 2018/01/11
- [Qemu-devel] [PULL 17/26] imx_fec: Add support for multiple Tx DMA rings, Peter Maydell, 2018/01/11
- [Qemu-devel] [PULL 02/26] linux-user: Add separate aarch64_be uname, Peter Maydell, 2018/01/11
- [Qemu-devel] [PULL 23/26] linux-user/arm/nwfpe: Check coprocessor number for FPA emulation, Peter Maydell, 2018/01/11
- [Qemu-devel] [PULL 22/26] hw/sd/pxa2xx_mmci: add read/write() trace events, Peter Maydell, 2018/01/11
- Re: [Qemu-devel] [PULL 00/26] target-arm queue, no-reply, 2018/01/11
- Re: [Qemu-devel] [PULL 00/26] target-arm queue, Peter Maydell, 2018/01/11