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[Qemu-devel] [PATCH 7/7] [RFC] i386: Add PCID to {Westmere, SandyBridge,
From: |
Eduardo Habkost |
Subject: |
[Qemu-devel] [PATCH 7/7] [RFC] i386: Add PCID to {Westmere, SandyBridge, IvyBridge}-IBRS |
Date: |
Tue, 9 Jan 2018 13:45:19 -0200 |
RFC NOTE: we need to confirm if all
Westmere/SandyBridge/IvyBridge CPUs out there support PCID,
before applying this patch.
RFC NOTE 2: in parallel, we are evaluating the possibility of
enabling PCID on the existing Westmere/SandyBridge/IvyBridge CPU
models, see
https://patchew.org/QEMU/address@hidden/
and
https://patchew.org/QEMU/address@hidden/
PCID was already available on Westmere, SandyBridge and
IvyBridge, but we can't easily add it to the existing CPU models
without breaking libvirt expectations about CPU model runnability
(a runnable CPU model shouldn't become runnable just because of a
machine-type or QEMU upgrade).
However, Westmere-IBRS, SandyBridge-IBRS and IvyBridge-IBRS are
new CPU models, so we can safely add PCID to them.
Note that PCID is not necessary to mitigate Meltdown and/or
Spectre, but it is really helpful to make performance not suffer
when enabling KPTI on guest kernels.
Cc: Jiri Denemark <address@hidden>
Suggested-by: Vincent Bernat <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>
---
target/i386/cpu.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 9c36f9bd44..ad79fbb111 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1119,6 +1119,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
+ /* Missing: CPUID_EXT_PCID */
.features[FEAT_1_ECX] =
CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
@@ -1148,7 +1149,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
.features[FEAT_1_ECX] =
CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
- CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
+ CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | CPUID_EXT_PCID,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
.features[FEAT_8000_0001_ECX] =
@@ -1173,6 +1174,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
+ /* Missing: CPUID_EXT_PCID */
.features[FEAT_1_ECX] =
CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
@@ -1209,7 +1211,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
- CPUID_EXT_SSE3,
+ CPUID_EXT_SSE3 | CPUID_EXT_PCID,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
CPUID_EXT2_SYSCALL,
@@ -1237,6 +1239,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
+ /* Missing: CPUID_EXT_PCID */
.features[FEAT_1_ECX] =
CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
@@ -1276,7 +1279,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
- CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
+ CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND |
CPUID_EXT_PCID,
.features[FEAT_7_0_EBX] =
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
CPUID_7_0_EBX_ERMS,
--
2.14.3
- [Qemu-devel] [PATCH 0/7] CPU model updates for CVE-2017-5715 (Spectre variant #2), Eduardo Habkost, 2018/01/09
- [Qemu-devel] [PATCH 1/7] i386: Change X86CPUDefinition::model_id to const char*, Eduardo Habkost, 2018/01/09
- [Qemu-devel] [PATCH 2/7] i386: Add support for SPEC_CTRL MSR, Eduardo Habkost, 2018/01/09
- [Qemu-devel] [PATCH 3/7] i386: Add spec-ctrl CPUID bit, Eduardo Habkost, 2018/01/09
- [Qemu-devel] [PATCH 4/7] i386: Add FEAT_8000_0008_EBX CPUID feature word, Eduardo Habkost, 2018/01/09
- [Qemu-devel] [PATCH 6/7] [RFC] i386: Add EPYC-IBPB CPU model, Eduardo Habkost, 2018/01/09
- [Qemu-devel] [PATCH 5/7] i386: Add new -IBRS versions of Intel CPU models, Eduardo Habkost, 2018/01/09
- [Qemu-devel] [PATCH 7/7] [RFC] i386: Add PCID to {Westmere, SandyBridge, IvyBridge}-IBRS,
Eduardo Habkost <=
- Re: [Qemu-devel] [PATCH 0/7] CPU model updates for CVE-2017-5715 (Spectre variant #2), no-reply, 2018/01/10
- Re: [Qemu-devel] [PATCH 0/7] CPU model updates for CVE-2017-5715 (Spectre variant #2), Eduardo Habkost, 2018/01/12
- Re: [Qemu-devel] [PATCH 0/7] CPU model updates for CVE-2017-5715 (Spectre variant #2), Eduardo Habkost, 2018/01/15