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[Qemu-devel] [PULL 07/13] target-arm: Don't check for "Thumb2 or M profi
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 07/13] target-arm: Don't check for "Thumb2 or M profile" for not-Thumb1 |
Date: |
Thu, 12 Oct 2017 17:03:30 +0100 |
The code which implements the Thumb1 split BL/BLX instructions
is guarded by a check on "not M or THUMB2". All we really need
to check here is "not THUMB2" (and we assume that elsewhere too,
eg in the ARCH(6T2) test that UNDEFs the Thumb2 insns).
This doesn't change behaviour because all M profile cores
have Thumb2 and so ARM_FEATURE_M implies ARM_FEATURE_THUMB2.
(v6M implements a very restricted subset of Thumb2, but we
can cross that bridge when we get to it with appropriate
feature bits.)
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
---
target/arm/translate.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 5c6f9fe..530a5c4 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9719,8 +9719,7 @@ static int disas_thumb2_insn(CPUARMState *env,
DisasContext *s, uint16_t insn_hw
int conds;
int logic_cc;
- if (!(arm_dc_feature(s, ARM_FEATURE_THUMB2)
- || arm_dc_feature(s, ARM_FEATURE_M))) {
+ if (!arm_dc_feature(s, ARM_FEATURE_THUMB2)) {
/* Thumb-1 cores may need to treat bl and blx as a pair of
16-bit instructions to get correct prefetch abort behavior. */
insn = insn_hw1;
--
2.7.4
- [Qemu-devel] [PULL 00/13] target-arm queue, Peter Maydell, 2017/10/12
- [Qemu-devel] [PULL 04/13] target/arm: Implement SG instruction, Peter Maydell, 2017/10/12
- [Qemu-devel] [PULL 06/13] target/arm: Implement secure function return, Peter Maydell, 2017/10/12
- [Qemu-devel] [PULL 01/13] watchdog/aspeed: fix variable type to store reload value, Peter Maydell, 2017/10/12
- [Qemu-devel] [PULL 09/13] target-arm: Simplify insn_crosses_page(), Peter Maydell, 2017/10/12
- [Qemu-devel] [PULL 03/13] target/arm: Add M profile secure MMU index values to get_a32_user_mem_index(), Peter Maydell, 2017/10/12
- [Qemu-devel] [PULL 12/13] nvic: Add missing 'break', Peter Maydell, 2017/10/12
- [Qemu-devel] [PULL 13/13] nvic: Fix miscalculation of offsets into ITNS array, Peter Maydell, 2017/10/12
- [Qemu-devel] [PULL 08/13] target/arm: Pull Thumb insn word loads up to top level, Peter Maydell, 2017/10/12
- [Qemu-devel] [PULL 02/13] arm: fix armv7m_init() declaration to match definition, Peter Maydell, 2017/10/12
- [Qemu-devel] [PULL 07/13] target-arm: Don't check for "Thumb2 or M profile" for not-Thumb1,
Peter Maydell <=
- [Qemu-devel] [PULL 05/13] target/arm: Implement BLXNS, Peter Maydell, 2017/10/12
- [Qemu-devel] [PULL 11/13] target/arm: Implement SG instruction corner cases, Peter Maydell, 2017/10/12
- [Qemu-devel] [PULL 10/13] target/arm: Support some Thumb insns being always unconditional, Peter Maydell, 2017/10/12
- Re: [Qemu-devel] [PULL 00/13] target-arm queue, Peter Maydell, 2017/10/16