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[Qemu-devel] [PULL 12/13] nvic: Add missing 'break'
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 12/13] nvic: Add missing 'break' |
Date: |
Thu, 12 Oct 2017 17:03:35 +0100 |
Coverity points out that we forgot the 'break' for
the SAU_CTRL write case (CID1381683). This has
no actual visible consequences because it happens
that the following case is effectively a no-op.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Richard Henderson <address@hidden>
---
hw/intc/armv7m_nvic.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 22d5e6e..a42961c 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -1447,6 +1447,7 @@ static void nvic_writel(NVICState *s, uint32_t offset,
uint32_t value,
return;
}
cpu->env.sau.ctrl = value & 3;
+ break;
case 0xdd4: /* SAU_TYPE */
if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
goto bad_offset;
--
2.7.4
- [Qemu-devel] [PULL 00/13] target-arm queue, Peter Maydell, 2017/10/12
- [Qemu-devel] [PULL 04/13] target/arm: Implement SG instruction, Peter Maydell, 2017/10/12
- [Qemu-devel] [PULL 06/13] target/arm: Implement secure function return, Peter Maydell, 2017/10/12
- [Qemu-devel] [PULL 01/13] watchdog/aspeed: fix variable type to store reload value, Peter Maydell, 2017/10/12
- [Qemu-devel] [PULL 09/13] target-arm: Simplify insn_crosses_page(), Peter Maydell, 2017/10/12
- [Qemu-devel] [PULL 03/13] target/arm: Add M profile secure MMU index values to get_a32_user_mem_index(), Peter Maydell, 2017/10/12
- [Qemu-devel] [PULL 12/13] nvic: Add missing 'break',
Peter Maydell <=
- [Qemu-devel] [PULL 13/13] nvic: Fix miscalculation of offsets into ITNS array, Peter Maydell, 2017/10/12
- [Qemu-devel] [PULL 08/13] target/arm: Pull Thumb insn word loads up to top level, Peter Maydell, 2017/10/12
- [Qemu-devel] [PULL 02/13] arm: fix armv7m_init() declaration to match definition, Peter Maydell, 2017/10/12
- [Qemu-devel] [PULL 07/13] target-arm: Don't check for "Thumb2 or M profile" for not-Thumb1, Peter Maydell, 2017/10/12
- [Qemu-devel] [PULL 05/13] target/arm: Implement BLXNS, Peter Maydell, 2017/10/12
- [Qemu-devel] [PULL 11/13] target/arm: Implement SG instruction corner cases, Peter Maydell, 2017/10/12
- [Qemu-devel] [PULL 10/13] target/arm: Support some Thumb insns being always unconditional, Peter Maydell, 2017/10/12
- Re: [Qemu-devel] [PULL 00/13] target-arm queue, Peter Maydell, 2017/10/16