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[Qemu-devel] [PULL 24/30] armv7m: Allow SHCSR writes to change pending a
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 24/30] armv7m: Allow SHCSR writes to change pending and active bits |
Date: |
Mon, 27 Feb 2017 18:04:53 +0000 |
Implement the NVIC SHCSR write behaviour which allows pending and
active status of some exceptions to be changed.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
---
hw/intc/armv7m_nvic.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 718b1a1..76097b4 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -755,8 +755,17 @@ static void nvic_writel(NVICState *s, uint32_t offset,
uint32_t value)
cpu->env.v7m.ccr = value;
break;
case 0xd24: /* System Handler Control. */
- /* TODO: Real hardware allows you to set/clear the active bits
- under some circumstances. We don't implement this. */
+ s->vectors[ARMV7M_EXCP_MEM].active = (value & (1 << 0)) != 0;
+ s->vectors[ARMV7M_EXCP_BUS].active = (value & (1 << 1)) != 0;
+ s->vectors[ARMV7M_EXCP_USAGE].active = (value & (1 << 3)) != 0;
+ s->vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0;
+ s->vectors[ARMV7M_EXCP_DEBUG].active = (value & (1 << 8)) != 0;
+ s->vectors[ARMV7M_EXCP_PENDSV].active = (value & (1 << 10)) != 0;
+ s->vectors[ARMV7M_EXCP_SYSTICK].active = (value & (1 << 11)) != 0;
+ s->vectors[ARMV7M_EXCP_USAGE].pending = (value & (1 << 12)) != 0;
+ s->vectors[ARMV7M_EXCP_MEM].pending = (value & (1 << 13)) != 0;
+ s->vectors[ARMV7M_EXCP_BUS].pending = (value & (1 << 14)) != 0;
+ s->vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0;
s->vectors[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0;
s->vectors[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0;
s->vectors[ARMV7M_EXCP_USAGE].enabled = (value & (1 << 18)) != 0;
--
2.7.4
- [Qemu-devel] [PULL 00/30] target-arm queue, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 18/30] armv7m: Remove unused armv7m_nvic_acknowledge_irq() return value, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 19/30] armv7m: Simpler and faster exception start, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 20/30] armv7m: VECTCLRACTIVE and VECTRESET are UNPREDICTABLE, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 21/30] armv7m: Extract "exception taken" code into functions, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 24/30] armv7m: Allow SHCSR writes to change pending and active bits,
Peter Maydell <=
- [Qemu-devel] [PULL 17/30] armv7m: Escalate exceptions to HardFault if necessary, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 15/30] armv7m: Fix condition check for taking exceptions, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 22/30] armv7m: Check exception return consistency, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 26/30] hw/sd: add card-reparenting function, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 16/30] arm: gic: Remove references to NVIC, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 01/30] target-arm: Implement BCM2835 hardware RNG, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 10/30] hw/arm/virt: Add a user option to disallow ITS instantiation, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 08/30] Add missing fp_access_check() to aarch64 crypto instructions, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 23/30] armv7m: Raise correct kind of UsageFault for attempts to execute ARM code, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 07/30] hw/arm/virt: fix cpu object reference leak, Peter Maydell, 2017/02/27