[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 19/30] armv7m: Simpler and faster exception start
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 19/30] armv7m: Simpler and faster exception start |
Date: |
Mon, 27 Feb 2017 18:04:48 +0000 |
From: Michael Davidsaver <address@hidden>
All the places in armv7m_cpu_do_interrupt() which pend an
exception in the NVIC are doing so for synchronous
exceptions. We know that we will always take some
exception in this case, so we can just acknowledge it
immediately, rather than returning and then immediately
being called again because the NVIC has raised its outbound
IRQ line.
Signed-off-by: Michael Davidsaver <address@hidden>
[PMM: tweaked commit message; added DEBUG to the set of
exceptions we handle immediately, since it is synchronous
when it results from the BKPT instruction]
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
---
target/arm/helper.c | 15 +++++++++------
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 85d1364..664f030 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6110,22 +6110,22 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
case EXCP_UDEF:
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
env->v7m.cfsr |= R_V7M_CFSR_UNDEFINSTR_MASK;
- return;
+ break;
case EXCP_NOCP:
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
env->v7m.cfsr |= R_V7M_CFSR_NOCP_MASK;
- return;
+ break;
case EXCP_SWI:
/* The PC already points to the next instruction. */
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
- return;
+ break;
case EXCP_PREFETCH_ABORT:
case EXCP_DATA_ABORT:
/* TODO: if we implemented the MPU registers, this is where we
* should set the MMFAR, etc from exception.fsr and exception.vaddress.
*/
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
- return;
+ break;
case EXCP_BKPT:
if (semihosting_enabled()) {
int nr;
@@ -6140,9 +6140,8 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
}
}
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
- return;
+ break;
case EXCP_IRQ:
- armv7m_nvic_acknowledge_irq(env->nvic);
break;
case EXCP_EXCEPTION_EXIT:
do_v7m_exception_exit(env);
@@ -6152,6 +6151,10 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
return; /* Never happens. Keep compiler happy. */
}
+ armv7m_nvic_acknowledge_irq(env->nvic);
+
+ qemu_log_mask(CPU_LOG_INT, "... as %d\n", env->v7m.exception);
+
/* Align stack pointer if the guest wants that */
if ((env->regs[13] & 4) && (env->v7m.ccr & R_V7M_CCR_STKALIGN_MASK)) {
env->regs[13] -= 4;
--
2.7.4
- [Qemu-devel] [PULL 00/30] target-arm queue, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 18/30] armv7m: Remove unused armv7m_nvic_acknowledge_irq() return value, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 19/30] armv7m: Simpler and faster exception start,
Peter Maydell <=
- [Qemu-devel] [PULL 20/30] armv7m: VECTCLRACTIVE and VECTRESET are UNPREDICTABLE, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 21/30] armv7m: Extract "exception taken" code into functions, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 24/30] armv7m: Allow SHCSR writes to change pending and active bits, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 17/30] armv7m: Escalate exceptions to HardFault if necessary, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 15/30] armv7m: Fix condition check for taking exceptions, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 22/30] armv7m: Check exception return consistency, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 26/30] hw/sd: add card-reparenting function, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 16/30] arm: gic: Remove references to NVIC, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 01/30] target-arm: Implement BCM2835 hardware RNG, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 10/30] hw/arm/virt: Add a user option to disallow ITS instantiation, Peter Maydell, 2017/02/27