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[Qemu-devel] [PULL 09/13] target/arm: Abstract out pbit/wbit tests in AR
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 09/13] target/arm: Abstract out pbit/wbit tests in ARM ldr/str decode |
Date: |
Tue, 7 Feb 2017 18:37:21 +0000 |
In the ARM ldr/str decode path, rather than directly testing
"insn & (1 << 21)" and "insn & (1 << 24)", abstract these
bits out into wbit and pbit local flags. (We will want to
do more tests against them to determine whether we need to
provide syndrome information.)
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
---
target/arm/translate.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 493c627..175b4c1 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -8782,6 +8782,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int
insn)
} else {
int address_offset;
bool load = insn & (1 << 20);
+ bool wbit = insn & (1 << 21);
+ bool pbit = insn & (1 << 24);
bool doubleword = false;
/* Misc load/store */
rn = (insn >> 16) & 0xf;
@@ -8799,8 +8801,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int
insn)
}
addr = load_reg(s, rn);
- if (insn & (1 << 24))
+ if (pbit) {
gen_add_datah_offset(s, insn, 0, addr);
+ }
address_offset = 0;
if (doubleword) {
@@ -8849,10 +8852,10 @@ static void disas_arm_insn(DisasContext *s, unsigned
int insn)
ensure correct behavior with overlapping index registers.
ldrd with base writeback is undefined if the
destination and index registers overlap. */
- if (!(insn & (1 << 24))) {
+ if (!pbit) {
gen_add_datah_offset(s, insn, address_offset, addr);
store_reg(s, rn, addr);
- } else if (insn & (1 << 21)) {
+ } else if (wbit) {
if (address_offset)
tcg_gen_addi_i32(addr, addr, address_offset);
store_reg(s, rn, addr);
--
2.7.4
- [Qemu-devel] [PULL 00/13] target-arm queue, Peter Maydell, 2017/02/07
- [Qemu-devel] [PULL 13/13] stellaris: Use the 'unimplemented' device for parts we don't implement, Peter Maydell, 2017/02/07
- [Qemu-devel] [PULL 12/13] hw/misc: New "unimplemented" sysbus device, Peter Maydell, 2017/02/07
- [Qemu-devel] [PULL 09/13] target/arm: Abstract out pbit/wbit tests in ARM ldr/str decode,
Peter Maydell <=
- [Qemu-devel] [PULL 10/13] target/arm: A32, T32: Create Instruction Syndromes for Data Aborts, Peter Maydell, 2017/02/07
- [Qemu-devel] [PULL 08/13] arm: Correctly handle watchpoints for BE32 CPUs, Peter Maydell, 2017/02/07
- [Qemu-devel] [PULL 11/13] stellaris: Document memory map and which SoC devices are unimplemented, Peter Maydell, 2017/02/07
- [Qemu-devel] [PULL 06/13] target/arm: Add cfgend parameter for ARM CPU selection., Peter Maydell, 2017/02/07
- [Qemu-devel] [PULL 04/13] sd: sdhci: check data length during dma_memory_read, Peter Maydell, 2017/02/07
- [Qemu-devel] [PULL 05/13] hw/arm/integratorcp: Support specifying features via -cpu, Peter Maydell, 2017/02/07
- [Qemu-devel] [PULL 07/13] Fix Thumb-1 BE32 execution and disassembly., Peter Maydell, 2017/02/07
- [Qemu-devel] [PULL 03/13] aspeed: add a watchdog controller, Peter Maydell, 2017/02/07
- [Qemu-devel] [PULL 02/13] wdt: Add Aspeed watchdog device model, Peter Maydell, 2017/02/07
- [Qemu-devel] [PULL 01/13] integratorcp: adding vmstate for save/restore, Peter Maydell, 2017/02/07