Re: [Qemu-devel] [PATCH V2 4/5] target-arm: Add support for PMU register PMINTENSET_EL1

[Wei Huang]

On 02/03/2017 07:30 AM, Peter Maydell wrote:
> On 31 January 2017 at 15:15, Wei Huang <address@hidden> wrote:
>> This patch adds access support for PMINTENSET_EL1.
>>
>> Signed-off-by: Wei Huang <address@hidden>
>> ---
>>  target/arm/cpu.h    |  2 +-
>>  target/arm/helper.c | 10 +++++++++-
>>  2 files changed, 10 insertions(+), 2 deletions(-)
>>
>> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
>> index ce02044..42aaea9 100644
>> --- a/target/arm/cpu.h
>> +++ b/target/arm/cpu.h
>> @@ -310,7 +310,7 @@ typedef struct CPUARMState {
>>          uint64_t c9_pmxevtyper; /* perf monitor event type */
>>          uint32_t c9_pmuserenr; /* perf monitor user enable */
>>          uint64_t c9_pmselr; /* perf monitor counter selection register */
>> -        uint32_t c9_pminten; /* perf monitor interrupt enables */
>> +        uint64_t c9_pminten; /* perf monitor interrupt enables */
>>          union { /* Memory attribute redirection */
>>              struct {
>>  #ifdef HOST_WORDS_BIGENDIAN
>> diff --git a/target/arm/helper.c b/target/arm/helper.c
>> index 6b8460a..b028042 100644
>> --- a/target/arm/helper.c
>> +++ b/target/arm/helper.c
>> @@ -1272,9 +1272,17 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
>>        .writefn = pmuserenr_write, .raw_writefn = raw_write },
>>      { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 
>> = 1,
>>        .access = PL1_RW, .accessfn = access_tpm,
>> -      .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
>> +      .type = ARM_CP_ALIAS,
>> +      .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pminten),
>>        .resetvalue = 0,
>>        .writefn = pmintenset_write, .raw_writefn = raw_write },
>> +    { .name = "PMINTENSET_EL1", .state = ARM_CP_STATE_AA64,
>> +      .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 1,
>> +      .access = PL1_RW, .accessfn = access_tpm,
>> +      .type = ARM_CP_IO,
>> +      .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
>> +      .writefn = pmintenset_write, .raw_writefn = raw_write,
>> +      .resetvalue = 0x0 },
>>      { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 
>> = 2,
>>        .access = PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS,
>>        .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
> 
> Add PMINTENCLR_EL1 as well, please.

It was already defined in target-arm/helper.c file. Could you elaborate
which part is missing?

    { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64,
      .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2,
      .access = PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS,
      .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
      .writefn = pmintenclr_write },




> 
> thanks
> -- PMM
>