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[Qemu-devel] [PATCH v2 19/20] target/arm: load two consecutive 64-bits v
From: |
Kirill Batuzov |
Subject: |
[Qemu-devel] [PATCH v2 19/20] target/arm: load two consecutive 64-bits vector regs as a 128-bit vector reg |
Date: |
Wed, 1 Feb 2017 15:18:21 +0300 |
ARM instruction set does not have loads to 128-bit vector register (q-regs).
Instead it can read several consecutive 64-bit vector register (d-regs)
which is used by GCC to load 128-bit registers from memory.
For vector operations to work we need to detect such loads and transform them
into 128-bit loads to 128-bit temporaries.
Signed-off-by: Kirill Batuzov <address@hidden>
---
target/arm/translate.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 90e14df..76f9927 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -4710,6 +4710,19 @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t
insn)
tcg_gen_addi_i32(addr, addr, 1 << size);
}
if (size == 3) {
+#ifdef TCG_TARGET_HAS_REG128
+ if (rd % 2 == 0 && nregs == 2) {
+ /* 128-bit load */
+ if (load) {
+ tcg_gen_qemu_ld_v128(cpu_Q[rd / 2], addr,
+ get_mem_index(s), MO_LE | MO_128);
+ } else {
+ tcg_gen_qemu_st_v128(cpu_Q[rd / 2], addr,
+ get_mem_index(s), MO_LE | MO_128);
+ }
+ break;
+ }
+#endif
tmp64 = tcg_temp_new_i64();
if (load) {
gen_aa32_ld64(s, tmp64, addr, get_mem_index(s));
--
2.1.4
- [Qemu-devel] [PATCH v2 06/20] tcg: use results of alias analysis in liveness analysis, (continued)
- [Qemu-devel] [PATCH v2 06/20] tcg: use results of alias analysis in liveness analysis, Kirill Batuzov, 2017/02/01
- [Qemu-devel] [PATCH v2 10/20] target/arm: use vector opcode to handle vadd.<size> instruction, Kirill Batuzov, 2017/02/01
- [Qemu-devel] [PATCH v2 11/20] tcg/i386: add support for vector opcodes, Kirill Batuzov, 2017/02/01
- [Qemu-devel] [PATCH v2 03/20] tcg: support representing vector type with smaller vector or scalar types, Kirill Batuzov, 2017/02/01
- [Qemu-devel] [PATCH v2 09/20] target/arm: support access to vector guest registers as globals, Kirill Batuzov, 2017/02/01
- [Qemu-devel] [PATCH v2 01/20] tcg: add support for 128bit vector type, Kirill Batuzov, 2017/02/01
- [Qemu-devel] [PATCH v2 04/20] tcg: add ld_v128, ld_v64, st_v128 and st_v64 opcodes, Kirill Batuzov, 2017/02/01
- [Qemu-devel] [PATCH v2 02/20] tcg: add support for 64bit vector type, Kirill Batuzov, 2017/02/01
- [Qemu-devel] [PATCH v2 05/20] tcg: add simple alias analysis, Kirill Batuzov, 2017/02/01
- [Qemu-devel] [PATCH v2 12/20] tcg/i386: support 64-bit vector operations, Kirill Batuzov, 2017/02/01
- [Qemu-devel] [PATCH v2 19/20] target/arm: load two consecutive 64-bits vector regs as a 128-bit vector reg,
Kirill Batuzov <=
- [Qemu-devel] [PATCH v2 16/20] tcg: introduce qemu_ld_v128 and qemu_st_v128 opcodes, Kirill Batuzov, 2017/02/01
- [Qemu-devel] [PATCH v2 13/20] tcg/i386: support remaining vector addition operations, Kirill Batuzov, 2017/02/01
- [Qemu-devel] [PATCH v2 18/20] tcg/i386: add support for qemu_ld_v128/qemu_st_v128 ops, Kirill Batuzov, 2017/02/01
- [Qemu-devel] [PATCH v2 14/20] tcg: do not rely on exact values of MO_BSWAP or MO_SIGN in backend, Kirill Batuzov, 2017/02/01
- Re: [Qemu-devel] [PATCH v2 00/20] Emulate guest vector operations with host vector operations, no-reply, 2017/02/01
- Re: [Qemu-devel] [PATCH v2 00/20] Emulate guest vector operations with host vector operations, no-reply, 2017/02/01