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[Qemu-devel] [PATCH v2 12/20] tcg/i386: support 64-bit vector operations
From: |
Kirill Batuzov |
Subject: |
[Qemu-devel] [PATCH v2 12/20] tcg/i386: support 64-bit vector operations |
Date: |
Wed, 1 Feb 2017 15:18:14 +0300 |
Signed-off-by: Kirill Batuzov <address@hidden>
---
tcg/i386/tcg-target.h | 1 +
tcg/i386/tcg-target.inc.c | 22 ++++++++++++++++++++++
2 files changed, 23 insertions(+)
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index b0704e8..755ebaa 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -31,6 +31,7 @@
#ifdef __x86_64__
# if defined(TARGET_WORDS_BIGENDIAN) == defined(HOST_WORDS_BIGENDIAN)
# define TCG_TARGET_HAS_REG128 1
+# define TCG_TARGET_HAS_REGV64 1
# endif
# ifdef TCG_TARGET_HAS_REG128
# define TCG_TARGET_REG_BITS 64
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
index 3e718f3..208bb81 100644
--- a/tcg/i386/tcg-target.inc.c
+++ b/tcg/i386/tcg-target.inc.c
@@ -390,6 +390,9 @@ static inline int tcg_target_const_match(tcg_target_long
val, TCGType type,
#define OPC_MOVDQU_M2R (0x6f | P_SSE_F30F) /* store 128-bit value */
#define OPC_MOVDQU_R2M (0x7f | P_SSE_F30F) /* load 128-bit value */
#define OPC_MOVDQA_R2R (0x6f | P_SSE_660F) /* reg-to-reg 128-bit mov */
+#define OPC_MOVQ_M2R (0x7e | P_SSE_F30F)
+#define OPC_MOVQ_R2M (0xd6 | P_SSE_660F)
+#define OPC_MOVQ_R2R (0x7e | P_SSE_F30F)
#define OPC_PADDD (0xfe | P_SSE_660F)
/* Group 1 opcode extensions for 0x80-0x83.
@@ -700,6 +703,15 @@ static inline void tcg_out_mov(TCGContext *s, TCGType type,
tcg_out_modrm(s, OPC_MOVDQA_R2R, ret, arg);
}
break;
+ case TCG_TYPE_V64:
+ ret -= TCG_REG_XMM0;
+ arg -= TCG_REG_XMM0;
+ if (have_avx) {
+ tcg_out_vex_modrm(s, OPC_MOVQ_R2R, ret, 15, arg);
+ } else {
+ tcg_out_modrm(s, OPC_MOVQ_R2R, ret, arg);
+ }
+ break;
case TCG_TYPE_I32:
case TCG_TYPE_I64:
opc = OPC_MOVL_GvEv + (type == TCG_TYPE_I64 ? P_REXW : 0);
@@ -788,6 +800,10 @@ static inline void tcg_out_ld(TCGContext *s, TCGType type,
TCGReg ret,
ret -= TCG_REG_XMM0;
tcg_out_modrm_offset(s, OPC_MOVDQU_M2R, ret, arg1, arg2);
break;
+ case TCG_TYPE_V64:
+ ret -= TCG_REG_XMM0;
+ tcg_out_modrm_offset(s, OPC_MOVQ_M2R, ret, arg1, arg2);
+ break;
case TCG_TYPE_I32:
case TCG_TYPE_I64:
opc = OPC_MOVL_GvEv + (type == TCG_TYPE_I64 ? P_REXW : 0);
@@ -807,6 +823,10 @@ static inline void tcg_out_st(TCGContext *s, TCGType type,
TCGReg arg,
arg -= TCG_REG_XMM0;
tcg_out_modrm_offset(s, OPC_MOVDQU_R2M, arg, arg1, arg2);
break;
+ case TCG_TYPE_V64:
+ arg -= TCG_REG_XMM0;
+ tcg_out_modrm_offset(s, OPC_MOVQ_R2M, arg, arg1, arg2);
+ break;
case TCG_TYPE_I32:
case TCG_TYPE_I64:
opc = OPC_MOVL_EvGv + (type == TCG_TYPE_I64 ? P_REXW : 0);
@@ -2407,6 +2427,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode
op)
case INDEX_op_ld_v128:
case INDEX_op_st_v128:
+ case INDEX_op_ld_v64:
+ case INDEX_op_st_v64:
return &V_r;
case INDEX_op_st8_i32:
--
2.1.4
- [Qemu-devel] [PATCH v2 17/20] softmmu: create helpers for vector loads, (continued)
- [Qemu-devel] [PATCH v2 17/20] softmmu: create helpers for vector loads, Kirill Batuzov, 2017/02/01
- [Qemu-devel] [PATCH v2 06/20] tcg: use results of alias analysis in liveness analysis, Kirill Batuzov, 2017/02/01
- [Qemu-devel] [PATCH v2 10/20] target/arm: use vector opcode to handle vadd.<size> instruction, Kirill Batuzov, 2017/02/01
- [Qemu-devel] [PATCH v2 11/20] tcg/i386: add support for vector opcodes, Kirill Batuzov, 2017/02/01
- [Qemu-devel] [PATCH v2 03/20] tcg: support representing vector type with smaller vector or scalar types, Kirill Batuzov, 2017/02/01
- [Qemu-devel] [PATCH v2 09/20] target/arm: support access to vector guest registers as globals, Kirill Batuzov, 2017/02/01
- [Qemu-devel] [PATCH v2 01/20] tcg: add support for 128bit vector type, Kirill Batuzov, 2017/02/01
- [Qemu-devel] [PATCH v2 04/20] tcg: add ld_v128, ld_v64, st_v128 and st_v64 opcodes, Kirill Batuzov, 2017/02/01
- [Qemu-devel] [PATCH v2 02/20] tcg: add support for 64bit vector type, Kirill Batuzov, 2017/02/01
- [Qemu-devel] [PATCH v2 05/20] tcg: add simple alias analysis, Kirill Batuzov, 2017/02/01
- [Qemu-devel] [PATCH v2 12/20] tcg/i386: support 64-bit vector operations,
Kirill Batuzov <=
- [Qemu-devel] [PATCH v2 19/20] target/arm: load two consecutive 64-bits vector regs as a 128-bit vector reg, Kirill Batuzov, 2017/02/01
- [Qemu-devel] [PATCH v2 16/20] tcg: introduce qemu_ld_v128 and qemu_st_v128 opcodes, Kirill Batuzov, 2017/02/01
- [Qemu-devel] [PATCH v2 13/20] tcg/i386: support remaining vector addition operations, Kirill Batuzov, 2017/02/01
- [Qemu-devel] [PATCH v2 18/20] tcg/i386: add support for qemu_ld_v128/qemu_st_v128 ops, Kirill Batuzov, 2017/02/01
- [Qemu-devel] [PATCH v2 14/20] tcg: do not rely on exact values of MO_BSWAP or MO_SIGN in backend, Kirill Batuzov, 2017/02/01
- Re: [Qemu-devel] [PATCH v2 00/20] Emulate guest vector operations with host vector operations, no-reply, 2017/02/01
- Re: [Qemu-devel] [PATCH v2 00/20] Emulate guest vector operations with host vector operations, no-reply, 2017/02/01