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[Qemu-devel] [PULL 02/36] block: m25p80: Add Quad Page Program 4byte
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 02/36] block: m25p80: Add Quad Page Program 4byte |
Date: |
Thu, 19 Jan 2017 14:09:21 +0000 |
From: Marcin Krzeminski <address@hidden>
Some flash chips have additional page program opcode that
takes only 4 byte address. This commit adds support
for such command in Qemu.
Signed-off-by: Marcin Krzeminski <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/block/m25p80.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index 4c5f8c3..4ad67ac 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -327,6 +327,7 @@ typedef enum {
PP4_4 = 0x3e,
DPP = 0xa2,
QPP = 0x32,
+ QPP_4 = 0x34,
ERASE_4K = 0x20,
ERASE4_4K = 0x21,
@@ -577,6 +578,7 @@ static inline int get_addr_length(Flash *s)
switch (s->cmd_in_progress) {
case PP4:
case PP4_4:
+ case QPP_4:
case READ4:
case QIOR4:
case ERASE4_4K:
@@ -610,6 +612,7 @@ static void complete_collecting_data(Flash *s)
switch (s->cmd_in_progress) {
case DPP:
case QPP:
+ case QPP_4:
case PP:
case PP4:
case PP4_4:
@@ -877,6 +880,7 @@ static void decode_new_cmd(Flash *s, uint32_t value)
case READ4:
case DPP:
case QPP:
+ case QPP_4:
case PP:
case PP4:
case PP4_4:
--
2.7.4
- [Qemu-devel] [PULL 30/36] hw/intc/arm_gicv3: Implement gicv3_cpuif_virt_update(), (continued)
- [Qemu-devel] [PULL 30/36] hw/intc/arm_gicv3: Implement gicv3_cpuif_virt_update(), Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 18/36] hw/arm/virt-acpi - reserve ECAM space as PNP0C02 device, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 15/36] aspeed/smc: extend tests for Command mode, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 12/36] aspeed/smc: adjust the size of the register region, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 03/36] block: m25p80: Introduce die erase command, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 36/36] hw/arm/virt: Add board property to enable EL2, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 35/36] target-arm: Enable EL2 feature bit on A53 and A57, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 07/36] aspeed/smc: remove call to reset in realize function, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 04/36] block: m25p80: Improve 1GiB Micron flash definition, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 05/36] target/arm: Handle VIRQ and VFIQ in arm_cpu_do_interrupt_aarch32(), Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 02/36] block: m25p80: Add Quad Page Program 4byte,
Peter Maydell <=
- [Qemu-devel] [PULL 01/36] arm: Uniquely name imx25 I2C buses., Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 17/36] arm: virt: Fix segmentation fault when specifying an unsupported CPU, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 14/36] aspeed/smc: reset flash after each test, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 13/36] aspeed/smc: handle SPI flash Command mode, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 09/36] aspeed/smc: rework the prototype of the AspeedSMCFlash helper routines, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 11/36] aspeed/smc: unfold the AspeedSMCController array, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 06/36] target/arm: Implement DBGVCR32_EL2 system register, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 10/36] aspeed/smc: autostrap CE0/1 configuration, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 16/36] aspeed: use first FMC flash as a boot ROM, Peter Maydell, 2017/01/19