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[Qemu-devel] [PULL 10/36] aspeed/smc: autostrap CE0/1 configuration
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 10/36] aspeed/smc: autostrap CE0/1 configuration |
Date: |
Thu, 19 Jan 2017 14:09:29 +0000 |
From: Cédric Le Goater <address@hidden>
On the AST2500 SoC, the FMC controller flash type is fixed to SPI for
CE0 and CE1 and 4BYTE mode is autodetected for CE0.
On the AST2400 SoC, the FMC controller flash type and 4BYTE mode are
strapped with register SCU70. We use the default settings from the
palmetto-bmc machine for now.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Reviewed-by: Andrew Jeffery <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/ssi/aspeed_smc.c | 32 +++++++++++++++++++++++++++-----
1 file changed, 27 insertions(+), 5 deletions(-)
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
index 9b31d5d..3bd381b 100644
--- a/hw/ssi/aspeed_smc.c
+++ b/hw/ssi/aspeed_smc.c
@@ -39,11 +39,14 @@
#define CONF_ENABLE_W2 18
#define CONF_ENABLE_W1 17
#define CONF_ENABLE_W0 16
-#define CONF_FLASH_TYPE4 9
-#define CONF_FLASH_TYPE3 7
-#define CONF_FLASH_TYPE2 5
-#define CONF_FLASH_TYPE1 3
-#define CONF_FLASH_TYPE0 1
+#define CONF_FLASH_TYPE4 8
+#define CONF_FLASH_TYPE3 6
+#define CONF_FLASH_TYPE2 4
+#define CONF_FLASH_TYPE1 2
+#define CONF_FLASH_TYPE0 0
+#define CONF_FLASH_TYPE_NOR 0x0
+#define CONF_FLASH_TYPE_NAND 0x1
+#define CONF_FLASH_TYPE_SPI 0x2
/* CE Control Register */
#define R_CE_CTRL (0x04 / 4)
@@ -436,6 +439,25 @@ static void aspeed_smc_reset(DeviceState *d)
s->regs[R_SEG_ADDR0 + i] =
aspeed_smc_segment_to_reg(&s->ctrl->segments[i]);
}
+
+ /* HW strapping for AST2500 FMC controllers */
+ if (s->ctrl->segments == aspeed_segments_ast2500_fmc) {
+ /* flash type is fixed to SPI for CE0 and CE1 */
+ s->regs[s->r_conf] |= (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0);
+ s->regs[s->r_conf] |= (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE1);
+
+ /* 4BYTE mode is autodetected for CE0. Let's force it to 1 for
+ * now */
+ s->regs[s->r_ce_ctrl] |= (1 << (CTRL_EXTENDED0));
+ }
+
+ /* HW strapping for AST2400 FMC controllers (SCU70). Let's use the
+ * configuration of the palmetto-bmc machine */
+ if (s->ctrl->segments == aspeed_segments_fmc) {
+ s->regs[s->r_conf] |= (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0);
+
+ s->regs[s->r_ce_ctrl] |= (1 << (CTRL_EXTENDED0));
+ }
}
static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size)
--
2.7.4
- [Qemu-devel] [PULL 04/36] block: m25p80: Improve 1GiB Micron flash definition, (continued)
- [Qemu-devel] [PULL 04/36] block: m25p80: Improve 1GiB Micron flash definition, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 05/36] target/arm: Handle VIRQ and VFIQ in arm_cpu_do_interrupt_aarch32(), Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 02/36] block: m25p80: Add Quad Page Program 4byte, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 01/36] arm: Uniquely name imx25 I2C buses., Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 17/36] arm: virt: Fix segmentation fault when specifying an unsupported CPU, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 14/36] aspeed/smc: reset flash after each test, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 13/36] aspeed/smc: handle SPI flash Command mode, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 09/36] aspeed/smc: rework the prototype of the AspeedSMCFlash helper routines, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 11/36] aspeed/smc: unfold the AspeedSMCController array, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 06/36] target/arm: Implement DBGVCR32_EL2 system register, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 10/36] aspeed/smc: autostrap CE0/1 configuration,
Peter Maydell <=
- [Qemu-devel] [PULL 16/36] aspeed: use first FMC flash as a boot ROM, Peter Maydell, 2017/01/19