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[Qemu-devel] [PATCH 34/65] target-tilegx: Use clz and ctz opcodes
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 34/65] target-tilegx: Use clz and ctz opcodes |
Date: |
Fri, 23 Dec 2016 20:00:11 -0800 |
Signed-off-by: Richard Henderson <address@hidden>
---
target/tilegx/helper.c | 10 ----------
target/tilegx/helper.h | 2 --
target/tilegx/translate.c | 4 ++--
3 files changed, 2 insertions(+), 14 deletions(-)
diff --git a/target/tilegx/helper.c b/target/tilegx/helper.c
index b4fba9c..b6f5e29 100644
--- a/target/tilegx/helper.c
+++ b/target/tilegx/helper.c
@@ -55,16 +55,6 @@ void helper_ext01_ics(CPUTLGState *env)
}
}
-uint64_t helper_cntlz(uint64_t arg)
-{
- return clz64(arg);
-}
-
-uint64_t helper_cnttz(uint64_t arg)
-{
- return ctz64(arg);
-}
-
uint64_t helper_pcnt(uint64_t arg)
{
return ctpop64(arg);
diff --git a/target/tilegx/helper.h b/target/tilegx/helper.h
index 9281d0f..bab303a 100644
--- a/target/tilegx/helper.h
+++ b/target/tilegx/helper.h
@@ -1,7 +1,5 @@
DEF_HELPER_2(exception, noreturn, env, i32)
DEF_HELPER_1(ext01_ics, void, env)
-DEF_HELPER_FLAGS_1(cntlz, TCG_CALL_NO_RWG_SE, i64, i64)
-DEF_HELPER_FLAGS_1(cnttz, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_FLAGS_1(pcnt, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_FLAGS_1(revbits, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_FLAGS_3(shufflebytes, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64)
diff --git a/target/tilegx/translate.c b/target/tilegx/translate.c
index 9c734ee..8a2df1b 100644
--- a/target/tilegx/translate.c
+++ b/target/tilegx/translate.c
@@ -608,12 +608,12 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned
opext,
switch (opext) {
case OE_RR_X0(CNTLZ):
case OE_RR_Y0(CNTLZ):
- gen_helper_cntlz(tdest, tsrca);
+ tcg_gen_clzi_tl(tdest, tsrca, TARGET_LONG_BITS);
mnemonic = "cntlz";
break;
case OE_RR_X0(CNTTZ):
case OE_RR_Y0(CNTTZ):
- gen_helper_cnttz(tdest, tsrca);
+ tcg_gen_ctzi_tl(tdest, tsrca, TARGET_LONG_BITS);
mnemonic = "cnttz";
break;
case OE_RR_X0(FSINGLE_PACK1):
--
2.9.3
- [Qemu-devel] [PATCH 26/65] disas/ppc: Handle popcnt and cnttz, (continued)
- [Qemu-devel] [PATCH 26/65] disas/ppc: Handle popcnt and cnttz, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 22/65] tcg: Pass the opcode width to target_parse_constraint, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 27/65] target-alpha: Use the ctz and clz opcodes, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 29/65] target-microblaze: Use clz opcode, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 30/65] target-mips: Use clz opcode, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 24/65] tcg: Add clz and ctz opcodes, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 28/65] target-cris: Use clz opcode, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 36/65] target-unicore32: Use clz opcode, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 32/65] target-ppc: Use clz and ctz opcodes, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 31/65] target-openrisc: Use clz and ctz opcodes, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 34/65] target-tilegx: Use clz and ctz opcodes,
Richard Henderson <=
- [Qemu-devel] [PATCH 33/65] target-s390x: Use clz opcode, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 35/65] target-tricore: Use clz opcode, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 38/65] target-arm: Use clz opcode, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 39/65] target-i386: Use clz and ctz opcodes, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 41/65] tcg/aarch64: Handle ctz and clz opcodes, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 43/65] tcg/mips: Handle clz opcode, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 37/65] target-xtensa: Use clz opcode, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 44/65] tcg/s390: Handle clz opcode, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 40/65] tcg/ppc: Handle ctz and clz opcodes, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 42/65] tcg/arm: Handle ctz and clz opcodes, Richard Henderson, 2016/12/23