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[Qemu-devel] [PATCH 30/65] target-mips: Use clz opcode
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 30/65] target-mips: Use clz opcode |
Date: |
Fri, 23 Dec 2016 20:00:07 -0800 |
Cc: Yongbok Kim <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/mips/helper.h | 7 -------
target/mips/op_helper.c | 22 ----------------------
target/mips/translate.c | 23 ++++++++++++++++-------
3 files changed, 16 insertions(+), 36 deletions(-)
diff --git a/target/mips/helper.h b/target/mips/helper.h
index 666936c..60efa01 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -20,13 +20,6 @@ DEF_HELPER_4(scd, tl, env, tl, tl, int)
#endif
#endif
-DEF_HELPER_FLAGS_1(clo, TCG_CALL_NO_RWG_SE, tl, tl)
-DEF_HELPER_FLAGS_1(clz, TCG_CALL_NO_RWG_SE, tl, tl)
-#ifdef TARGET_MIPS64
-DEF_HELPER_FLAGS_1(dclo, TCG_CALL_NO_RWG_SE, tl, tl)
-DEF_HELPER_FLAGS_1(dclz, TCG_CALL_NO_RWG_SE, tl, tl)
-#endif
-
DEF_HELPER_3(muls, tl, env, tl, tl)
DEF_HELPER_3(mulsu, tl, env, tl, tl)
DEF_HELPER_3(macc, tl, env, tl, tl)
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index 7af4c2f..11d781f 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -103,28 +103,6 @@ HELPER_ST(sd, stq, uint64_t)
#endif
#undef HELPER_ST
-target_ulong helper_clo (target_ulong arg1)
-{
- return clo32(arg1);
-}
-
-target_ulong helper_clz (target_ulong arg1)
-{
- return clz32(arg1);
-}
-
-#if defined(TARGET_MIPS64)
-target_ulong helper_dclo (target_ulong arg1)
-{
- return clo64(arg1);
-}
-
-target_ulong helper_dclz (target_ulong arg1)
-{
- return clz64(arg1);
-}
-#endif /* TARGET_MIPS64 */
-
/* 64 bits arithmetic for 32 bits hosts */
static inline uint64_t get_HILO(CPUMIPSState *env)
{
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 8deffa1..7f8ecf4 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -3626,29 +3626,38 @@ static void gen_cl (DisasContext *ctx, uint32_t opc,
/* Treat as NOP. */
return;
}
- t0 = tcg_temp_new();
+ t0 = cpu_gpr[rd];
gen_load_gpr(t0, rs);
+
switch (opc) {
case OPC_CLO:
case R6_OPC_CLO:
- gen_helper_clo(cpu_gpr[rd], t0);
+#if defined(TARGET_MIPS64)
+ case OPC_DCLO:
+ case R6_OPC_DCLO:
+#endif
+ tcg_gen_not_tl(t0, t0);
break;
+ }
+
+ switch (opc) {
+ case OPC_CLO:
+ case R6_OPC_CLO:
case OPC_CLZ:
case R6_OPC_CLZ:
- gen_helper_clz(cpu_gpr[rd], t0);
+ tcg_gen_ext32u_tl(t0, t0);
+ tcg_gen_clzi_tl(t0, t0, TARGET_LONG_BITS);
+ tcg_gen_subi_tl(t0, t0, TARGET_LONG_BITS - 32);
break;
#if defined(TARGET_MIPS64)
case OPC_DCLO:
case R6_OPC_DCLO:
- gen_helper_dclo(cpu_gpr[rd], t0);
- break;
case OPC_DCLZ:
case R6_OPC_DCLZ:
- gen_helper_dclz(cpu_gpr[rd], t0);
+ tcg_gen_clzi_i64(t0, t0, 64);
break;
#endif
}
- tcg_temp_free(t0);
}
/* Godson integer instructions */
--
2.9.3
- [Qemu-devel] [PATCH 19/65] tcg/optimize: Fold movcond 0/1 into setcond, (continued)
- [Qemu-devel] [PATCH 19/65] tcg/optimize: Fold movcond 0/1 into setcond, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 21/65] tcg: Transition flat op_defs array to a target callback, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 20/65] tcg: Add markup for output requires new register, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 23/65] tcg: Allow an operand to be matching or a constant, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 16/65] target-mips: Use the new extract op, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 25/65] disas/i386.c: Handle tzcnt, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 26/65] disas/ppc: Handle popcnt and cnttz, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 22/65] tcg: Pass the opcode width to target_parse_constraint, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 27/65] target-alpha: Use the ctz and clz opcodes, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 29/65] target-microblaze: Use clz opcode, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 30/65] target-mips: Use clz opcode,
Richard Henderson <=
- [Qemu-devel] [PATCH 24/65] tcg: Add clz and ctz opcodes, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 28/65] target-cris: Use clz opcode, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 36/65] target-unicore32: Use clz opcode, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 32/65] target-ppc: Use clz and ctz opcodes, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 31/65] target-openrisc: Use clz and ctz opcodes, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 34/65] target-tilegx: Use clz and ctz opcodes, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 33/65] target-s390x: Use clz opcode, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 35/65] target-tricore: Use clz opcode, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 38/65] target-arm: Use clz opcode, Richard Henderson, 2016/12/23
- [Qemu-devel] [PATCH 39/65] target-i386: Use clz and ctz opcodes, Richard Henderson, 2016/12/23