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[Qemu-devel] [PATCH 09/15] tcg/s390: Implement field extraction opcodes
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 09/15] tcg/s390: Implement field extraction opcodes |
Date: |
Sat, 15 Oct 2016 20:37:44 -0700 |
Cc: Alexander Graf <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/s390/tcg-target.h | 12 +++++++-----
tcg/s390/tcg-target.inc.c | 13 ++++++++++++-
2 files changed, 19 insertions(+), 6 deletions(-)
diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
index 9583df4..cf8fbfd 100644
--- a/tcg/s390/tcg-target.h
+++ b/tcg/s390/tcg-target.h
@@ -66,7 +66,7 @@ typedef enum TCGReg {
#define TCG_TARGET_HAS_nand_i32 0
#define TCG_TARGET_HAS_nor_i32 0
#define TCG_TARGET_HAS_deposit_i32 1
-#define TCG_TARGET_HAS_extract_i32 0
+#define TCG_TARGET_HAS_extract_i32 1
#define TCG_TARGET_HAS_sextract_i32 0
#define TCG_TARGET_HAS_movcond_i32 1
#define TCG_TARGET_HAS_add2_i32 1
@@ -97,7 +97,7 @@ typedef enum TCGReg {
#define TCG_TARGET_HAS_nand_i64 0
#define TCG_TARGET_HAS_nor_i64 0
#define TCG_TARGET_HAS_deposit_i64 1
-#define TCG_TARGET_HAS_extract_i64 0
+#define TCG_TARGET_HAS_extract_i64 1
#define TCG_TARGET_HAS_sextract_i64 0
#define TCG_TARGET_HAS_movcond_i64 1
#define TCG_TARGET_HAS_add2_i64 1
@@ -107,9 +107,11 @@ typedef enum TCGReg {
#define TCG_TARGET_HAS_muluh_i64 0
#define TCG_TARGET_HAS_mulsh_i64 0
-extern bool tcg_target_deposit_valid(int ofs, int len);
-#define TCG_TARGET_deposit_i32_valid tcg_target_deposit_valid
-#define TCG_TARGET_deposit_i64_valid tcg_target_deposit_valid
+extern bool tcg_target_have_gen_inst(void);
+#define TCG_TARGET_deposit_i32_valid(o,l) tcg_target_have_gen_inst()
+#define TCG_TARGET_deposit_i64_valid(o,l) tcg_target_have_gen_inst()
+#define TCG_TARGET_extract_i32_valid(o,l) tcg_target_have_gen_inst()
+#define TCG_TARGET_extract_i64_valid(o,l) tcg_target_have_gen_inst()
/* used for function call generation */
#define TCG_REG_CALL_STACK TCG_REG_R15
diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c
index 253d4a0..fa9e144 100644
--- a/tcg/s390/tcg-target.inc.c
+++ b/tcg/s390/tcg-target.inc.c
@@ -1250,7 +1250,7 @@ static void tgen_movcond(TCGContext *s, TCGType type,
TCGCond c, TCGReg dest,
}
}
-bool tcg_target_deposit_valid(int ofs, int len)
+bool tcg_target_have_gen_inst(void)
{
return (facilities & FACILITY_GEN_INST_EXT) != 0;
}
@@ -1263,6 +1263,12 @@ static void tgen_deposit(TCGContext *s, TCGReg dest,
TCGReg src,
tcg_out_risbg(s, dest, src, msb, lsb, ofs, 0);
}
+static void tgen_extract(TCGContext *s, TCGReg dest, TCGReg src,
+ int ofs, int len)
+{
+ tcg_out_risbg(s, dest, src, 64 - len, 63, 64 - ofs, 1);
+}
+
static void tgen_gotoi(TCGContext *s, int cc, tcg_insn_unit *dest)
{
ptrdiff_t off = dest - s->code_ptr;
@@ -2169,6 +2175,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode
opc,
OP_32_64(deposit):
tgen_deposit(s, args[0], args[2], args[3], args[4]);
break;
+ OP_32_64(extract):
+ tgen_extract(s, args[0], args[1], args[2], args[3]);
+ break;
case INDEX_op_mb:
/* The host memory model is quite strong, we simply need to
@@ -2238,6 +2247,7 @@ static const TCGTargetOpDef s390_op_defs[] = {
{ INDEX_op_setcond_i32, { "r", "r", "rC" } },
{ INDEX_op_movcond_i32, { "r", "r", "rC", "r", "0" } },
{ INDEX_op_deposit_i32, { "r", "0", "r" } },
+ { INDEX_op_extract_i32, { "r", "r" } },
{ INDEX_op_qemu_ld_i32, { "r", "L" } },
{ INDEX_op_qemu_ld_i64, { "r", "L" } },
@@ -2299,6 +2309,7 @@ static const TCGTargetOpDef s390_op_defs[] = {
{ INDEX_op_setcond_i64, { "r", "r", "rC" } },
{ INDEX_op_movcond_i64, { "r", "r", "rC", "r", "0" } },
{ INDEX_op_deposit_i64, { "r", "0", "r" } },
+ { INDEX_op_extract_i64, { "r", "r" } },
{ INDEX_op_mb, { } },
{ -1 },
--
2.7.4
- [Qemu-devel] [PATCH 03/15] tcg/aarch64: Implement field extraction opcodes, (continued)
- [Qemu-devel] [PATCH 03/15] tcg/aarch64: Implement field extraction opcodes, Richard Henderson, 2016/10/15
- [Qemu-devel] [PATCH 02/15] tcg: Minor adjustments to deposit expanders, Richard Henderson, 2016/10/15
- [Qemu-devel] [PATCH 04/15] tcg/arm: Move isa detection to tcg-target.h, Richard Henderson, 2016/10/15
- [Qemu-devel] [PATCH 05/15] tcg/arm: Implement field extraction opcodes, Richard Henderson, 2016/10/15
- [Qemu-devel] [PATCH 06/15] tcg/i386: Implement field extraction opcodes, Richard Henderson, 2016/10/15
- [Qemu-devel] [PATCH 07/15] tcg/mips: Implement field extraction opcodes, Richard Henderson, 2016/10/15
- [Qemu-devel] [PATCH 08/15] tcg/ppc: Implement field extraction opcodes, Richard Henderson, 2016/10/15
- [Qemu-devel] [PATCH 09/15] tcg/s390: Implement field extraction opcodes,
Richard Henderson <=
- [Qemu-devel] [PATCH 10/15] target-alpha: Use deposit and extract ops, Richard Henderson, 2016/10/15
- [Qemu-devel] [PATCH 11/15] target-arm: Use tcg_gen_*extract, Richard Henderson, 2016/10/15
- [Qemu-devel] [PATCH 12/15] target-i386: Use tcg_gen_extract_tl, Richard Henderson, 2016/10/15
- [Qemu-devel] [PATCH 13/15] target-mips: Use tcg_gen_extract_*, Richard Henderson, 2016/10/15
- [Qemu-devel] [PATCH 14/15] target-ppc: Use tcg_gen_extract_*, Richard Henderson, 2016/10/15