[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH 12/15] target-i386: Use tcg_gen_extract_tl
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 12/15] target-i386: Use tcg_gen_extract_tl |
Date: |
Sat, 15 Oct 2016 20:37:47 -0700 |
Three places where it was easy to identify a right-shift
followed by an extract or and-with-immediate.
Signed-off-by: Richard Henderson <address@hidden>
---
target-i386/translate.c | 45 +++++++++++++++++++++++----------------------
1 file changed, 23 insertions(+), 22 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 2f60e9c..4a3014c 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -383,8 +383,7 @@ static void gen_op_mov_reg_v(TCGMemOp ot, int reg, TCGv t0)
static inline void gen_op_mov_v_reg(TCGMemOp ot, TCGv t0, int reg)
{
if (ot == MO_8 && byte_reg_is_xH(reg)) {
- tcg_gen_shri_tl(t0, cpu_regs[reg - 4], 8);
- tcg_gen_ext8u_tl(t0, t0);
+ tcg_gen_extract_tl(t0, cpu_regs[reg - 4], 8, 8);
} else {
tcg_gen_mov_tl(t0, cpu_regs[reg]);
}
@@ -3715,8 +3714,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s,
int b,
/* Extract the LEN into a mask. Lengths larger than
operand size get all ones. */
- tcg_gen_shri_tl(cpu_A0, cpu_regs[s->vex_v], 8);
- tcg_gen_ext8u_tl(cpu_A0, cpu_A0);
+ tcg_gen_extract_tl(cpu_A0, cpu_regs[s->vex_v], 8, 8);
tcg_gen_movcond_tl(TCG_COND_LEU, cpu_A0, cpu_A0, bound,
cpu_A0, bound);
tcg_temp_free(bound);
@@ -3867,9 +3865,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s,
int b,
gen_compute_eflags(s);
}
carry_in = cpu_tmp0;
- tcg_gen_shri_tl(carry_in, cpu_cc_src,
- ctz32(b == 0x1f6 ? CC_C : CC_O));
- tcg_gen_andi_tl(carry_in, carry_in, 1);
+ tcg_gen_extract_tl(carry_in, cpu_cc_src,
+ ctz32(b == 0x1f6 ? CC_C : CC_O), 1);
}
switch (ot) {
@@ -5340,21 +5337,25 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
rm = (modrm & 7) | REX_B(s);
if (mod == 3) {
- gen_op_mov_v_reg(ot, cpu_T0, rm);
- switch (s_ot) {
- case MO_UB:
- tcg_gen_ext8u_tl(cpu_T0, cpu_T0);
- break;
- case MO_SB:
- tcg_gen_ext8s_tl(cpu_T0, cpu_T0);
- break;
- case MO_UW:
- tcg_gen_ext16u_tl(cpu_T0, cpu_T0);
- break;
- default:
- case MO_SW:
- tcg_gen_ext16s_tl(cpu_T0, cpu_T0);
- break;
+ if (s_ot == MO_SB && byte_reg_is_xH(rm)) {
+ tcg_gen_sextract_tl(cpu_T0, cpu_regs[rm - 4], 8, 8);
+ } else {
+ gen_op_mov_v_reg(ot, cpu_T0, rm);
+ switch (s_ot) {
+ case MO_UB:
+ tcg_gen_ext8u_tl(cpu_T0, cpu_T0);
+ break;
+ case MO_SB:
+ tcg_gen_ext8s_tl(cpu_T0, cpu_T0);
+ break;
+ case MO_UW:
+ tcg_gen_ext16u_tl(cpu_T0, cpu_T0);
+ break;
+ default:
+ case MO_SW:
+ tcg_gen_ext16s_tl(cpu_T0, cpu_T0);
+ break;
+ }
}
gen_op_mov_reg_v(d_ot, reg, cpu_T0);
} else {
--
2.7.4
- Re: [Qemu-devel] [PATCH 02/15] tcg: Minor adjustments to deposit expanders, (continued)
- [Qemu-devel] [PATCH 04/15] tcg/arm: Move isa detection to tcg-target.h, Richard Henderson, 2016/10/15
- [Qemu-devel] [PATCH 05/15] tcg/arm: Implement field extraction opcodes, Richard Henderson, 2016/10/15
- [Qemu-devel] [PATCH 06/15] tcg/i386: Implement field extraction opcodes, Richard Henderson, 2016/10/15
- [Qemu-devel] [PATCH 07/15] tcg/mips: Implement field extraction opcodes, Richard Henderson, 2016/10/15
- [Qemu-devel] [PATCH 08/15] tcg/ppc: Implement field extraction opcodes, Richard Henderson, 2016/10/15
- [Qemu-devel] [PATCH 09/15] tcg/s390: Implement field extraction opcodes, Richard Henderson, 2016/10/15
- [Qemu-devel] [PATCH 10/15] target-alpha: Use deposit and extract ops, Richard Henderson, 2016/10/15
- [Qemu-devel] [PATCH 11/15] target-arm: Use tcg_gen_*extract, Richard Henderson, 2016/10/15
- [Qemu-devel] [PATCH 12/15] target-i386: Use tcg_gen_extract_tl,
Richard Henderson <=
- [Qemu-devel] [PATCH 13/15] target-mips: Use tcg_gen_extract_*, Richard Henderson, 2016/10/15
- [Qemu-devel] [PATCH 14/15] target-ppc: Use tcg_gen_extract_*, Richard Henderson, 2016/10/15
- [Qemu-devel] [PATCH 15/15] target-s390: Use tcg_gen_extract_i64, Richard Henderson, 2016/10/15
- Re: [Qemu-devel] [PATCH 00/15] tcg field extract primitives, no-reply, 2016/10/16