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[Qemu-devel] [PATCH v5 22/35] target-i386: emulate LOCK'ed XADD using at
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v5 22/35] target-i386: emulate LOCK'ed XADD using atomic helper |
Date: |
Sun, 9 Oct 2016 18:41:53 -0500 |
From: "Emilio G. Cota" <address@hidden>
[rth: Move load of reg value to common location.]
Signed-off-by: Emilio G. Cota <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target-i386/translate.c | 15 ++++++++++-----
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 17a37a3..049b1e4 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -5135,19 +5135,24 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
mod = (modrm >> 6) & 3;
+ gen_op_mov_v_reg(ot, cpu_T0, reg);
if (mod == 3) {
rm = (modrm & 7) | REX_B(s);
- gen_op_mov_v_reg(ot, cpu_T0, reg);
gen_op_mov_v_reg(ot, cpu_T1, rm);
tcg_gen_add_tl(cpu_T0, cpu_T0, cpu_T1);
gen_op_mov_reg_v(ot, reg, cpu_T1);
gen_op_mov_reg_v(ot, rm, cpu_T0);
} else {
gen_lea_modrm(env, s, modrm);
- gen_op_mov_v_reg(ot, cpu_T0, reg);
- gen_op_ld_v(s, ot, cpu_T1, cpu_A0);
- tcg_gen_add_tl(cpu_T0, cpu_T0, cpu_T1);
- gen_op_st_v(s, ot, cpu_T0, cpu_A0);
+ if (s->prefix & PREFIX_LOCK) {
+ tcg_gen_atomic_fetch_add_tl(cpu_T1, cpu_A0, cpu_T0,
+ s->mem_index, ot | MO_LE);
+ tcg_gen_add_tl(cpu_T0, cpu_T0, cpu_T1);
+ } else {
+ gen_op_ld_v(s, ot, cpu_T1, cpu_A0);
+ tcg_gen_add_tl(cpu_T0, cpu_T0, cpu_T1);
+ gen_op_st_v(s, ot, cpu_T0, cpu_A0);
+ }
gen_op_mov_reg_v(ot, reg, cpu_T1);
}
gen_op_update2_cc();
--
2.7.4
- Re: [Qemu-devel] [PATCH v5 13/35] tcg: Add atomic helpers, (continued)
[Qemu-devel] [PATCH v5 17/35] target-i386: emulate LOCK'ed cmpxchg using cmpxchg helpers, Richard Henderson, 2016/10/09
[Qemu-devel] [PATCH v5 16/35] tcg: Emit barriers with parallel_cpus, Richard Henderson, 2016/10/09
[Qemu-devel] [PATCH v5 20/35] target-i386: emulate LOCK'ed NOT using atomic helper, Richard Henderson, 2016/10/09
[Qemu-devel] [PATCH v5 19/35] target-i386: emulate LOCK'ed INC using atomic helper, Richard Henderson, 2016/10/09
[Qemu-devel] [PATCH v5 18/35] target-i386: emulate LOCK'ed OP instructions using atomic helpers, Richard Henderson, 2016/10/09
[Qemu-devel] [PATCH v5 23/35] target-i386: emulate LOCK'ed BTX ops using atomic helpers, Richard Henderson, 2016/10/09
[Qemu-devel] [PATCH v5 21/35] target-i386: emulate LOCK'ed NEG using cmpxchg helper, Richard Henderson, 2016/10/09
[Qemu-devel] [PATCH v5 22/35] target-i386: emulate LOCK'ed XADD using atomic helper,
Richard Henderson <=
[Qemu-devel] [PATCH v5 24/35] target-i386: emulate XCHG using atomic helper, Richard Henderson, 2016/10/09
[Qemu-devel] [PATCH v5 25/35] target-i386: remove helper_lock(), Richard Henderson, 2016/10/09
[Qemu-devel] [PATCH v5 26/35] tests: add atomic_add-bench, Richard Henderson, 2016/10/09
[Qemu-devel] [PATCH v5 27/35] target-arm: Rearrange aa32 load and store functions, Richard Henderson, 2016/10/09
[Qemu-devel] [PATCH v5 29/35] target-arm: emulate SWP with atomic_xchg helper, Richard Henderson, 2016/10/09
[Qemu-devel] [PATCH v5 31/35] linux-user: remove handling of ARM's EXCP_STREX, Richard Henderson, 2016/10/09
[Qemu-devel] [PATCH v5 32/35] linux-user: remove handling of aarch64's EXCP_STREX, Richard Henderson, 2016/10/09
[Qemu-devel] [PATCH v5 28/35] target-arm: emulate LL/SC using cmpxchg helpers, Richard Henderson, 2016/10/09
[Qemu-devel] [PATCH v5 30/35] target-arm: emulate aarch64's LL/SC using cmpxchg helpers, Richard Henderson, 2016/10/09
[Qemu-devel] [PATCH v5 34/35] target-alpha: Introduce MMU_PHYS_IDX, Richard Henderson, 2016/10/09