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[Qemu-devel] [PATCH 2/6] target-ppc: Implement darn instruction
From: |
Nikunj A Dadhania |
Subject: |
[Qemu-devel] [PATCH 2/6] target-ppc: Implement darn instruction |
Date: |
Sun, 7 Aug 2016 23:06:51 +0530 |
From: Ravi Bangoria <address@hidden>
darn: Deliver A Random Number
For both CRN and RRN, returning 64-bit random number.
Signed-off-by: Ravi Bangoria <address@hidden>
Signed-off-by: Nikunj A Dadhania <address@hidden>
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 14 ++++++++++++++
target-ppc/translate.c | 11 +++++++++++
3 files changed, 26 insertions(+)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 8eada2f..257bfca 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -50,6 +50,7 @@ DEF_HELPER_FLAGS_1(cnttzd, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_1(popcntd, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_2(bpermd, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_3(srad, tl, env, tl, tl)
+DEF_HELPER_1(darn, tl, i32)
#endif
DEF_HELPER_FLAGS_1(cntlsw32, TCG_CALL_NO_RWG_SE, i32, i32)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 552b2e0..2b9fe13 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -182,6 +182,20 @@ target_ulong helper_cnttzd(target_ulong t)
{
return ctz64(t);
}
+
+target_ulong helper_darn(uint32_t l)
+{
+ target_ulong r = UINT64_MAX;
+
+ if (l <= 2) {
+ do {
+ r = random() * random();
+ r &= l ? UINT64_MAX : UINT32_MAX;
+ } while (r == UINT64_MAX);
+ }
+
+ return r;
+}
#endif
#if defined(TARGET_PPC64)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 2a87d1a..6a79fc1 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -526,6 +526,8 @@ EXTRACT_HELPER(FPW, 16, 1);
/* addpcis */
EXTRACT_HELPER_DXFORM(DX, 10, 6, 6, 5, 16, 1, 1, 0, 0)
+/* darn */
+EXTRACT_HELPER(L, 16, 2);
/*** Jump target decoding ***/
/* Immediate address */
@@ -1893,6 +1895,14 @@ static void gen_cnttzd(DisasContext *ctx)
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
}
}
+
+/* darn */
+static void gen_darn(DisasContext *ctx)
+{
+ TCGv_i32 l = tcg_const_i32(L(ctx->opcode));
+ gen_helper_darn(cpu_gpr[rD(ctx->opcode)], l);
+ tcg_temp_free_i32(l);
+}
#endif
/*** Integer rotate ***/
@@ -6238,6 +6248,7 @@ GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801,
PPC_NONE, PPC2_ISA205),
GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE,
PPC2_PERM_ISA206),
#endif
--
2.7.4
- [Qemu-devel] [PATCH 0/6] POWER9 TCG enablements - part4, Nikunj A Dadhania, 2016/08/07
- [Qemu-devel] [PATCH 1/6] target-ppc: add xxspltib instruction, Nikunj A Dadhania, 2016/08/07
- [Qemu-devel] [PATCH 2/6] target-ppc: Implement darn instruction,
Nikunj A Dadhania <=
- Re: [Qemu-devel] [PATCH 2/6] target-ppc: Implement darn instruction, David Gibson, 2016/08/08
- Re: [Qemu-devel] [PATCH 2/6] target-ppc: Implement darn instruction, Nikunj A Dadhania, 2016/08/09
- Re: [Qemu-devel] [Qemu-ppc] [PATCH 2/6] target-ppc: Implement darn instruction, Nikunj A Dadhania, 2016/08/09
- Re: [Qemu-devel] [Qemu-ppc] [PATCH 2/6] target-ppc: Implement darn instruction, David Gibson, 2016/08/12
- Re: [Qemu-devel] [Qemu-ppc] [PATCH 2/6] target-ppc: Implement darn instruction, Nikunj A Dadhania, 2016/08/12
- Re: [Qemu-devel] [Qemu-ppc] [PATCH 2/6] target-ppc: Implement darn instruction, Thomas Huth, 2016/08/12