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Re: [Qemu-devel] [PATCH 25/32] ppc: Handle unconditional (always/never)
From: |
Benjamin Herrenschmidt |
Subject: |
Re: [Qemu-devel] [PATCH 25/32] ppc: Handle unconditional (always/never) traps at translation time |
Date: |
Wed, 27 Jul 2016 14:00:14 +1000 |
On Wed, 2016-07-27 at 12:33 +1000, David Gibson wrote:
>
> Should you be returning true here?
>
> Without it, IIUC, the functions below will generate the unconditional
> trap, then generate more code to actually test the condition and trap
> again.
You are right, we generate dead code, will fix.
Cheers,
Ben.
> >
> > + }
> > + return false;
> > +}
> > +
> > /* tw */
> > static void gen_tw(DisasContext *ctx)
> > {
> > - TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
> > + TCGv_i32 t0;
> > +
> > + if (check_unconditional_trap(ctx)) {
> > + return;
> > + }
> > + t0 = tcg_const_i32(TO(ctx->opcode));
> > gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)],
> > cpu_gpr[rB(ctx->opcode)],
> > t0);
> > tcg_temp_free_i32(t0);
> > @@ -3372,8 +3391,14 @@ static void gen_tw(DisasContext *ctx)
> > /* twi */
> > static void gen_twi(DisasContext *ctx)
> > {
> > - TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
> > - TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
> > + TCGv t0;
> > + TCGv_i32 t1;
> > +
> > + if (check_unconditional_trap(ctx)) {
> > + return;
> > + }
> > + t0 = tcg_const_tl(SIMM(ctx->opcode));
> > + t1 = tcg_const_i32(TO(ctx->opcode));
> > gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
> > tcg_temp_free(t0);
> > tcg_temp_free_i32(t1);
> > @@ -3383,7 +3408,12 @@ static void gen_twi(DisasContext *ctx)
> > /* td */
> > static void gen_td(DisasContext *ctx)
> > {
> > - TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
> > + TCGv_i32 t0;
> > +
> > + if (check_unconditional_trap(ctx)) {
> > + return;
> > + }
> > + t0 = tcg_const_i32(TO(ctx->opcode));
> > gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)],
> > cpu_gpr[rB(ctx->opcode)],
> > t0);
> > tcg_temp_free_i32(t0);
> > @@ -3392,8 +3422,14 @@ static void gen_td(DisasContext *ctx)
> > /* tdi */
> > static void gen_tdi(DisasContext *ctx)
> > {
> > - TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
> > - TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
> > + TCGv t0;
> > + TCGv_i32 t1;
> > +
> > + if (check_unconditional_trap(ctx)) {
> > + return;
> > + }
> > + t0 = tcg_const_tl(SIMM(ctx->opcode));
> > + t1 = tcg_const_i32(TO(ctx->opcode));
> > gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
> > tcg_temp_free(t0);
> > tcg_temp_free_i32(t1);
>
- Re: [Qemu-devel] [PATCH 26/32] ppc: Speed up dcbz, (continued)
- [Qemu-devel] [PATCH 32/32] ppc: Speed up load/store multiple, Benjamin Herrenschmidt, 2016/07/26
- [Qemu-devel] [PATCH 14/32] ppc: Don't update NIP in lmw/stmw/icbi, Benjamin Herrenschmidt, 2016/07/26
- [Qemu-devel] [PATCH 23/32] ppc: Don't update NIP in dcbz and lscbx, Benjamin Herrenschmidt, 2016/07/26
- [Qemu-devel] [PATCH 17/32] ppc: Fix source NIP on SLB related interrupts, Benjamin Herrenschmidt, 2016/07/26
- [Qemu-devel] [PATCH 25/32] ppc: Handle unconditional (always/never) traps at translation time, Benjamin Herrenschmidt, 2016/07/26
- Re: [Qemu-devel] [PATCH 01/32] ppc: Fix fault PC reporting for lve*/stve* VMX instructions, David Gibson, 2016/07/26