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[Qemu-devel] [RFC 17/30] target-i386: emulate LOCK'ed BTX ops using atom
From: |
Emilio G. Cota |
Subject: |
[Qemu-devel] [RFC 17/30] target-i386: emulate LOCK'ed BTX ops using atomic helpers |
Date: |
Mon, 27 Jun 2016 15:02:03 -0400 |
Signed-off-by: Emilio G. Cota <address@hidden>
---
target-i386/translate.c | 76 +++++++++++++++++++++++++++++++++----------------
1 file changed, 52 insertions(+), 24 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 7df744e..b76b0ae 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -1315,7 +1315,10 @@ glue(gen_atomic_, NAME)(TCGv ret, TCGv addr, TCGv reg,
TCGMemOp ot) \
#endif /* TARGET_X86_64 */
GEN_ATOMIC_HELPER(fetch_add)
+GEN_ATOMIC_HELPER(fetch_and)
+GEN_ATOMIC_HELPER(fetch_or)
GEN_ATOMIC_HELPER(fetch_sub)
+GEN_ATOMIC_HELPER(fetch_xor)
GEN_ATOMIC_HELPER(add_fetch)
GEN_ATOMIC_HELPER(and_fetch)
@@ -6796,32 +6799,57 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
}
bt_op:
tcg_gen_andi_tl(cpu_T1, cpu_T1, (1 << (3 + ot)) - 1);
- tcg_gen_shr_tl(cpu_tmp4, cpu_T0, cpu_T1);
- switch(op) {
- case 0:
- break;
- case 1:
- tcg_gen_movi_tl(cpu_tmp0, 1);
- tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T1);
- tcg_gen_or_tl(cpu_T0, cpu_T0, cpu_tmp0);
- break;
- case 2:
- tcg_gen_movi_tl(cpu_tmp0, 1);
- tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T1);
- tcg_gen_andc_tl(cpu_T0, cpu_T0, cpu_tmp0);
- break;
- default:
- case 3:
+ if (s->prefix & PREFIX_LOCK) {
+ TCGv t0;
+
+ t0 = tcg_temp_new();
tcg_gen_movi_tl(cpu_tmp0, 1);
tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T1);
- tcg_gen_xor_tl(cpu_T0, cpu_T0, cpu_tmp0);
- break;
- }
- if (op != 0) {
- if (mod != 3) {
- gen_op_st_v(s, ot, cpu_T0, cpu_A0);
- } else {
- gen_op_mov_reg_v(ot, rm, cpu_T0);
+ switch (op) {
+ case 1:
+ gen_atomic_fetch_or(t0, cpu_A0, cpu_tmp0, ot);
+ tcg_gen_or_tl(cpu_T0, t0, cpu_tmp0);
+ break;
+ case 2:
+ tcg_gen_not_tl(cpu_tmp0, cpu_tmp0);
+ gen_atomic_fetch_and(t0, cpu_A0, cpu_tmp0, ot);
+ tcg_gen_and_tl(cpu_T0, t0, cpu_tmp0);
+ break;
+ case 3:
+ gen_atomic_fetch_xor(t0, cpu_A0, cpu_tmp0, ot);
+ tcg_gen_xor_tl(cpu_T0, t0, cpu_tmp0);
+ break;
+ }
+ tcg_gen_shr_tl(cpu_tmp4, t0, cpu_T1);
+ tcg_temp_free(t0);
+ } else {
+ tcg_gen_shr_tl(cpu_tmp4, cpu_T0, cpu_T1);
+ switch (op) {
+ case 0:
+ break;
+ case 1:
+ tcg_gen_movi_tl(cpu_tmp0, 1);
+ tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T1);
+ tcg_gen_or_tl(cpu_T0, cpu_T0, cpu_tmp0);
+ break;
+ case 2:
+ tcg_gen_movi_tl(cpu_tmp0, 1);
+ tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T1);
+ tcg_gen_andc_tl(cpu_T0, cpu_T0, cpu_tmp0);
+ break;
+ default:
+ case 3:
+ tcg_gen_movi_tl(cpu_tmp0, 1);
+ tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T1);
+ tcg_gen_xor_tl(cpu_T0, cpu_T0, cpu_tmp0);
+ break;
+ }
+ if (op != 0) {
+ if (mod != 3) {
+ gen_op_st_v(s, ot, cpu_T0, cpu_A0);
+ } else {
+ gen_op_mov_reg_v(ot, rm, cpu_T0);
+ }
}
}
--
2.5.0
- [Qemu-devel] [RFC 13/30] target-i386: emulate LOCK'ed INC using atomic helper, (continued)
- [Qemu-devel] [RFC 13/30] target-i386: emulate LOCK'ed INC using atomic helper, Emilio G. Cota, 2016/06/27
- [Qemu-devel] [RFC 15/30] target-i386: emulate LOCK'ed NEG using cmpxchg helper, Emilio G. Cota, 2016/06/27
- [Qemu-devel] [RFC 27/30] target-arm: emulate aarch64's LL/SC using cmpxchg helpers, Emilio G. Cota, 2016/06/27
- [Qemu-devel] [RFC 25/30] helper: add DEF_HELPER_6, Emilio G. Cota, 2016/06/27
- [Qemu-devel] [RFC 16/30] target-i386: emulate LOCK'ed XADD using atomic helper, Emilio G. Cota, 2016/06/27
- [Qemu-devel] [RFC 23/30] target-arm: add atomic_xchg helper, Emilio G. Cota, 2016/06/27
- [Qemu-devel] [RFC 22/30] target-arm: emulate LL/SC using cmpxchg helpers, Emilio G. Cota, 2016/06/27
- [Qemu-devel] [RFC 29/30] linux-user: remove handling of aarch64's EXCP_STREX, Emilio G. Cota, 2016/06/27
- [Qemu-devel] [RFC 20/30] target-i386: remove helper_lock(), Emilio G. Cota, 2016/06/27
- [Qemu-devel] [RFC 26/30] target-arm: add cmpxchg helpers for aarch64, Emilio G. Cota, 2016/06/27
- [Qemu-devel] [RFC 17/30] target-i386: emulate LOCK'ed BTX ops using atomic helpers,
Emilio G. Cota <=
- [Qemu-devel] [RFC 24/30] target-arm: emulate SWP with atomic_xchg helper, Emilio G. Cota, 2016/06/27
- [Qemu-devel] [RFC 30/30] target-arm: remove EXCP_STREX + cpu_exclusive_{test, info}, Emilio G. Cota, 2016/06/27
- [Qemu-devel] [RFC 18/30] target-i386: emulate XCHG using atomic helper, Emilio G. Cota, 2016/06/27
- [Qemu-devel] [RFC 28/30] linux-user: remove handling of ARM's EXCP_STREX, Emilio G. Cota, 2016/06/27
- [Qemu-devel] [RFC 21/30] target-arm: add cmpxchg helpers, Emilio G. Cota, 2016/06/27
- [Qemu-devel] [RFC 19/30] tests: add atomic_add-bench, Emilio G. Cota, 2016/06/27
- Re: [Qemu-devel] [RFC 00/30] cmpxchg-based emulation of atomics, LluĂs Vilanova, 2016/06/28