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[Qemu-devel] [PATCH 01/25] target-openrisc: Always enable OPENRISC_DISAS
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 01/25] target-openrisc: Always enable OPENRISC_DISAS |
Date: |
Mon, 13 Jun 2016 16:58:01 -0700 |
Avoids warnings from unused variables etc.
Reviewed-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target-openrisc/translate.c | 20 ++++----------------
1 file changed, 4 insertions(+), 16 deletions(-)
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index c08876b..97e8665 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@@ -34,14 +34,9 @@
#include "trace-tcg.h"
#include "exec/log.h"
-
-#define OPENRISC_DISAS
-
-#ifdef OPENRISC_DISAS
-# define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
-#else
-# define LOG_DIS(...) do { } while (0)
-#endif
+/* Set to 0 to completely disable. */
+#define OPENRISC_DISAS CPU_LOG_TB_IN_ASM
+#define LOG_DIS(...) qemu_log_mask(OPENRISC_DISAS, ## __VA_ARGS__)
typedef struct DisasContext {
TranslationBlock *tb;
@@ -715,9 +710,7 @@ static void dec_misc(DisasContext *dc, uint32_t insn)
{
uint32_t op0, op1;
uint32_t ra, rb, rd;
-#ifdef OPENRISC_DISAS
uint32_t L6, K5;
-#endif
uint32_t I16, I5, I11, N26, tmp;
TCGMemOp mop;
@@ -726,10 +719,8 @@ static void dec_misc(DisasContext *dc, uint32_t insn)
ra = extract32(insn, 16, 5);
rb = extract32(insn, 11, 5);
rd = extract32(insn, 21, 5);
-#ifdef OPENRISC_DISAS
L6 = extract32(insn, 5, 6);
K5 = extract32(insn, 0, 5);
-#endif
I16 = extract32(insn, 0, 16);
I5 = extract32(insn, 21, 5);
I11 = extract32(insn, 0, 11);
@@ -1326,13 +1317,10 @@ static void dec_compi(DisasContext *dc, uint32_t insn)
static void dec_sys(DisasContext *dc, uint32_t insn)
{
uint32_t op0;
-#ifdef OPENRISC_DISAS
uint32_t K16;
-#endif
+
op0 = extract32(insn, 16, 10);
-#ifdef OPENRISC_DISAS
K16 = extract32(insn, 0, 16);
-#endif
switch (op0) {
case 0x000: /* l.sys */
--
2.5.5
- [Qemu-devel] [PATCH 00/25] target-openrisc improvements, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 01/25] target-openrisc: Always enable OPENRISC_DISAS,
Richard Henderson <=
- [Qemu-devel] [PATCH 06/25] target-openrisc: Put SR[OVE] in TB flags, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 05/25] target-openrisc: Use movcond where appropriate, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 08/25] target-openrisc: Set flags on helpers, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 03/25] target-openrisc: Invert the decoding in dec_calc, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 04/25] target-openrisc: Keep SR_F in a separate variable, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 07/25] target-openrisc: Keep SR_CY and SR_OV in a separate variables, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 02/25] target-openrisc: Streamline arithmetic and OVE, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 12/25] target-openrisc: Enable m[tf]spr from user mode, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 13/25] target-openrisc: Enable trap, csync, msync, psync for user mode, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 11/25] target-openrisc: Rationalize immediate extraction, Richard Henderson, 2016/06/13