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[Qemu-devel] [PATCH 05/25] target-openrisc: Use movcond where appropriat
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 05/25] target-openrisc: Use movcond where appropriate |
Date: |
Mon, 13 Jun 2016 16:58:05 -0700 |
Reviewed-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target-openrisc/translate.c | 28 ++++++++++++++--------------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index 2421b92..48bd5f7 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@@ -219,12 +219,16 @@ static void gen_jump(DisasContext *dc, uint32_t imm,
uint32_t reg, uint32_t op0)
case 0x03: /* l.bnf */
case 0x04: /* l.bf */
{
- TCGLabel *lab = gen_new_label();
- tcg_gen_movi_tl(jmp_pc, dc->pc+8);
- tcg_gen_brcondi_i32(op0 == 0x03 ? TCG_COND_EQ : TCG_COND_NE,
- cpu_sr_f, SR_F, lab);
- tcg_gen_movi_tl(jmp_pc, tmp_pc);
- gen_set_label(lab);
+ TCGv t_next = tcg_const_tl(dc->pc + 8);
+ TCGv t_true = tcg_const_tl(tmp_pc);
+ TCGv t_zero = tcg_const_tl(0);
+
+ tcg_gen_movcond_tl(op0 == 0x03 ? TCG_COND_EQ : TCG_COND_NE,
+ jmp_pc, cpu_sr_f, t_zero, t_true, t_next);
+
+ tcg_temp_free(t_next);
+ tcg_temp_free(t_true);
+ tcg_temp_free(t_zero);
}
break;
case 0x11: /* l.jr */
@@ -507,14 +511,10 @@ static void dec_calc(DisasContext *dc, uint32_t insn)
case 0xe: /* l.cmov */
LOG_DIS("l.cmov r%d, r%d, r%d\n", rd, ra, rb);
{
- TCGLabel *lab = gen_new_label();
- TCGv res = tcg_temp_local_new();
- tcg_gen_mov_tl(res, cpu_R[rb]);
- tcg_gen_brcondi_tl(TCG_COND_NE, cpu_sr_f, SR_F, lab);
- tcg_gen_mov_tl(res, cpu_R[ra]);
- gen_set_label(lab);
- tcg_gen_mov_tl(cpu_R[rd], res);
- tcg_temp_free(res);
+ TCGv zero = tcg_const_tl(0);
+ tcg_gen_movcond_tl(TCG_COND_NE, cpu_R[rd], cpu_sr_f, zero,
+ cpu_R[ra], cpu_R[rb]);
+ tcg_temp_free(zero);
}
return;
--
2.5.5
- [Qemu-devel] [PATCH 00/25] target-openrisc improvements, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 01/25] target-openrisc: Always enable OPENRISC_DISAS, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 06/25] target-openrisc: Put SR[OVE] in TB flags, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 05/25] target-openrisc: Use movcond where appropriate,
Richard Henderson <=
- [Qemu-devel] [PATCH 08/25] target-openrisc: Set flags on helpers, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 03/25] target-openrisc: Invert the decoding in dec_calc, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 04/25] target-openrisc: Keep SR_F in a separate variable, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 07/25] target-openrisc: Keep SR_CY and SR_OV in a separate variables, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 02/25] target-openrisc: Streamline arithmetic and OVE, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 12/25] target-openrisc: Enable m[tf]spr from user mode, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 13/25] target-openrisc: Enable trap, csync, msync, psync for user mode, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 11/25] target-openrisc: Rationalize immediate extraction, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 14/25] target-openrisc: Implement muld, muldu, macu, msbu, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 19/25] target-openrisc: Tidy ppc/npc implementation, Richard Henderson, 2016/06/13