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[Qemu-devel] [PATCH v6 19/26] intel_iommu: Add support for Extended Inte
From: |
Peter Xu |
Subject: |
[Qemu-devel] [PATCH v6 19/26] intel_iommu: Add support for Extended Interrupt Mode |
Date: |
Thu, 5 May 2016 11:25:54 +0800 |
From: Jan Kiszka <address@hidden>
As neither QEMU nor KVM support more than 255 CPUs so far, this is
simple: we only need to switch the destination ID translation in
vtd_remap_irq_get if EIME is set.
Once CFI support is there, it will have to take EIM into account as
well. So far, nothing to do for this.
This patch allows to use x2APIC in split irqchip mode of KVM.
Signed-off-by: Jan Kiszka <address@hidden>
---
hw/i386/intel_iommu.c | 16 +++++++++-------
hw/i386/intel_iommu_internal.h | 2 ++
include/hw/i386/intel_iommu.h | 1 +
3 files changed, 12 insertions(+), 7 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index dc0e4ba..1e57125 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -922,6 +922,7 @@ static void vtd_interrupt_remap_table_setup(IntelIOMMUState
*s)
value = vtd_get_quad_raw(s, DMAR_IRTA_REG);
s->intr_size = 1UL << ((value & VTD_IRTA_SIZE_MASK) + 1);
s->intr_root = value & VTD_IRTA_ADDR_MASK;
+ s->intr_eime = value & VTD_IRTA_EIME;
/* Notify global invalidation */
vtd_iec_notify_all(s, true, 0, 0);
@@ -2056,11 +2057,13 @@ static int vtd_remap_irq_get(IntelIOMMUState *iommu,
uint16_t index, VTDIrq *irq
irq->trigger_mode = irte.trigger_mode;
irq->vector = irte.vector;
irq->delivery_mode = irte.delivery_mode;
- /* Not support EIM yet: please refer to vt-d 9.10 DST bits */
+ irq->dest = irte.dest_id;
+ if (!iommu->intr_eime) {
#define VTD_IR_APIC_DEST_MASK (0xff00ULL)
#define VTD_IR_APIC_DEST_SHIFT (8)
- irq->dest = (irte.dest_id & VTD_IR_APIC_DEST_MASK) >> \
- VTD_IR_APIC_DEST_SHIFT;
+ irq->dest = (irq->dest & VTD_IR_APIC_DEST_MASK) >>
+ VTD_IR_APIC_DEST_SHIFT;
+ }
irq->dest_mode = irte.dest_mode;
irq->redir_hint = irte.redir_hint;
@@ -2330,7 +2333,7 @@ static void vtd_init(IntelIOMMUState *s)
s->ecap = VTD_ECAP_QI | VTD_ECAP_IRO;
if (ms->iommu_intr) {
- s->ecap |= VTD_ECAP_IR;
+ s->ecap |= VTD_ECAP_IR | VTD_ECAP_EIM;
}
vtd_reset_context_cache(s);
@@ -2384,10 +2387,9 @@ static void vtd_init(IntelIOMMUState *s)
vtd_define_quad(s, DMAR_FRCD_REG_0_2, 0, 0, 0x8000000000000000ULL);
/*
- * Interrupt remapping registers, not support extended interrupt
- * mode for now.
+ * Interrupt remapping registers.
*/
- vtd_define_quad(s, DMAR_IRTA_REG, 0, 0xfffffffffffff00fULL, 0);
+ vtd_define_quad(s, DMAR_IRTA_REG, 0, 0xfffffffffffff80fULL, 0);
}
/* Should not reset address_spaces when reset because devices will still use
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index 10c20fe..72b0114 100644
--- a/hw/i386/intel_iommu_internal.h
+++ b/hw/i386/intel_iommu_internal.h
@@ -176,6 +176,7 @@
/* IRTA_REG */
#define VTD_IRTA_ADDR_MASK (VTD_HAW_MASK ^ 0xfffULL)
+#define VTD_IRTA_EIME (1ULL << 11)
#define VTD_IRTA_SIZE_MASK (0xfULL)
/* ECAP_REG */
@@ -184,6 +185,7 @@
#define VTD_ECAP_QI (1ULL << 1)
/* Interrupt Remapping support */
#define VTD_ECAP_IR (1ULL << 3)
+#define VTD_ECAP_EIM (1ULL << 4)
/* CAP_REG */
/* (offset >> 4) << 24 */
diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h
index 4fe92cf..c0c5819 100644
--- a/include/hw/i386/intel_iommu.h
+++ b/include/hw/i386/intel_iommu.h
@@ -261,6 +261,7 @@ struct IntelIOMMUState {
bool intr_enabled; /* Whether guest enabled IR */
dma_addr_t intr_root; /* Interrupt remapping table pointer */
uint32_t intr_size; /* Number of IR table entries */
+ bool intr_eime; /* Extended interrupt mode enabled */
QLIST_HEAD(, VTD_IEC_Notifier) iec_notifiers; /* IEC notify list */
};
--
2.4.11
- [Qemu-devel] [PATCH v6 09/26] intel_iommu: add IR translation faults defines, (continued)
- [Qemu-devel] [PATCH v6 09/26] intel_iommu: add IR translation faults defines, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 10/26] intel_iommu: Add support for PCI MSI remap, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 11/26] q35: ioapic: add support for emulated IOAPIC IR, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 12/26] ioapic: introduce ioapic_entry_parse() helper, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 13/26] intel_iommu: add support for split irqchip, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 14/26] q35: add "intremap" parameter to enable IR, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 15/26] intel_iommu: introduce IEC notifiers, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 16/26] ioapic: register VT-d IEC invalidate notifier, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 17/26] ioapic: keep RO bits for IOAPIC entry, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 18/26] ioapic: clear remote irr bit for edge-triggered interrupts, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 19/26] intel_iommu: Add support for Extended Interrupt Mode,
Peter Xu <=
- [Qemu-devel] [PATCH v6 20/26] intel_iommu: add SID validation for IR, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 21/26] x86-iommu: introduce parent class, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 22/26] x86-iommu: replace existing VT-d hooks into X86 ones, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 23/26] kvm-irqchip: simplify kvm_irqchip_add_msi_route, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 25/26] kvm-irqchip: x86: add msi route notify fn, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 26/26] kvm-irqchip: do explicit commit when update irq, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 24/26] kvm-irqchip: i386: add hook for add/remove virq, Peter Xu, 2016/05/04