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[Qemu-devel] [PATCH v6 13/26] intel_iommu: add support for split irqchip
From: |
Peter Xu |
Subject: |
[Qemu-devel] [PATCH v6 13/26] intel_iommu: add support for split irqchip |
Date: |
Thu, 5 May 2016 11:25:48 +0800 |
In split irqchip mode, IOAPIC is working in user space, only update
kernel irq routes when entry changed. When IR is enabled, we directly
update the kernel with translated messages. It works just like a kernel
cache for the remapping entries.
Since KVM irqfd is using kernel gsi routes to deliver interrupts, as
long as we can support split irqchip, we will support irqfd as
well. Also, since kernel gsi routes will cache translated interrupts,
irqfd delivery will not suffer from any performance impact due to IR.
And, since we supported irqfd, vhost devices will be able to work
seamlessly with IR now. Logically this should contain both vhost-net and
vhost-user case.
Signed-off-by: Peter Xu <address@hidden>
---
include/hw/i386/intel_iommu.h | 2 ++
target-i386/kvm.c | 24 ++++++++++++++++++++++++
trace-events | 3 +++
3 files changed, 29 insertions(+)
diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h
index 5945670..5910e6f 100644
--- a/include/hw/i386/intel_iommu.h
+++ b/include/hw/i386/intel_iommu.h
@@ -25,6 +25,7 @@
#include "sysemu/dma.h"
#include "hw/i386/ioapic.h"
#include "hw/pci/msi.h"
+#include "hw/sysbus.h"
#define TYPE_INTEL_IOMMU_DEVICE "intel-iommu"
#define INTEL_IOMMU_DEVICE(obj) \
@@ -250,5 +251,6 @@ struct IntelIOMMUState {
VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devfn);
/* Get default IOMMU object */
IntelIOMMUState *vtd_iommu_get(void);
+int vtd_int_remap(void *iommu, MSIMessage *src, MSIMessage *dst);
#endif
diff --git a/target-i386/kvm.c b/target-i386/kvm.c
index 799fdfa..ea5387c 100644
--- a/target-i386/kvm.c
+++ b/target-i386/kvm.c
@@ -36,6 +36,7 @@
#include "hw/i386/apic.h"
#include "hw/i386/apic_internal.h"
#include "hw/i386/apic-msidef.h"
+#include "hw/i386/intel_iommu.h"
#include "exec/ioport.h"
#include "standard-headers/asm-x86/hyperv.h"
@@ -43,6 +44,7 @@
#include "hw/pci/msi.h"
#include "migration/migration.h"
#include "exec/memattrs.h"
+#include "trace.h"
//#define DEBUG_KVM
@@ -3327,6 +3329,28 @@ int kvm_device_msix_deassign(KVMState *s, uint32_t
dev_id)
int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
uint64_t address, uint32_t data, PCIDevice *dev)
{
+ IntelIOMMUState *iommu = vtd_iommu_get();
+
+ if (iommu) {
+ int ret;
+ MSIMessage src, dst;
+
+ src.address = route->u.msi.address_hi;
+ src.address <<= VTD_MSI_ADDR_HI_SHIFT;
+ src.address |= route->u.msi.address_lo;
+ src.data = route->u.msi.data;
+
+ ret = vtd_int_remap(iommu, &src, &dst);
+ if (ret) {
+ trace_kvm_x86_fixup_msi_error(route->gsi);
+ return 1;
+ }
+
+ route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
+ route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
+ route->u.msi.data = dst.data;
+ }
+
return 0;
}
diff --git a/trace-events b/trace-events
index 8350743..b03d310 100644
--- a/trace-events
+++ b/trace-events
@@ -1909,3 +1909,6 @@ aspeed_vic_update_fiq(int flags) "Raising FIQ: %d"
aspeed_vic_update_irq(int flags) "Raising IRQ: %d"
aspeed_vic_read(uint64_t offset, unsigned size, uint32_t value) "From 0x%"
PRIx64 " of size %u: 0x%" PRIx32
aspeed_vic_write(uint64_t offset, unsigned size, uint32_t data) "To 0x%"
PRIx64 " of size %u: 0x%" PRIx32
+
+# target-i386/kvm.c
+kvm_x86_fixup_msi_error(uint32_t gsi) "VT-d failed to remap interrupt for GSI
%" PRIu32
--
2.4.11
- [Qemu-devel] [PATCH v6 05/26] intel_iommu: define interrupt remap table addr register, (continued)
- [Qemu-devel] [PATCH v6 05/26] intel_iommu: define interrupt remap table addr register, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 06/26] intel_iommu: handle interrupt remap enable, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 07/26] intel_iommu: define several structs for IOMMU IR, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 08/26] intel_iommu: provide helper function vtd_get_iommu, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 09/26] intel_iommu: add IR translation faults defines, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 10/26] intel_iommu: Add support for PCI MSI remap, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 11/26] q35: ioapic: add support for emulated IOAPIC IR, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 12/26] ioapic: introduce ioapic_entry_parse() helper, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 13/26] intel_iommu: add support for split irqchip,
Peter Xu <=
- [Qemu-devel] [PATCH v6 14/26] q35: add "intremap" parameter to enable IR, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 15/26] intel_iommu: introduce IEC notifiers, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 16/26] ioapic: register VT-d IEC invalidate notifier, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 17/26] ioapic: keep RO bits for IOAPIC entry, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 18/26] ioapic: clear remote irr bit for edge-triggered interrupts, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 19/26] intel_iommu: Add support for Extended Interrupt Mode, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 20/26] intel_iommu: add SID validation for IR, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 21/26] x86-iommu: introduce parent class, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 22/26] x86-iommu: replace existing VT-d hooks into X86 ones, Peter Xu, 2016/05/04