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[Qemu-devel] [PULL 10/36] exec-all.h: Document tlb_set_page_with_attrs,
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 10/36] exec-all.h: Document tlb_set_page_with_attrs, tlb_set_page |
Date: |
Thu, 21 Jan 2016 14:56:03 +0000 |
Add documentation comments for tlb_set_page_with_attrs()
and tlb_set_page().
Signed-off-by: Peter Maydell <address@hidden>
Acked-by: Edgar E. Iglesias <address@hidden>
---
include/exec/exec-all.h | 34 +++++++++++++++++++++++++++++++---
1 file changed, 31 insertions(+), 3 deletions(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 9be0165..caa78a9 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -144,12 +144,40 @@ void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong
addr, ...);
* MMU indexes.
*/
void tlb_flush_by_mmuidx(CPUState *cpu, ...);
-void tlb_set_page(CPUState *cpu, target_ulong vaddr,
- hwaddr paddr, int prot,
- int mmu_idx, target_ulong size);
+/**
+ * tlb_set_page_with_attrs:
+ * @cpu: CPU to add this TLB entry for
+ * @vaddr: virtual address of page to add entry for
+ * @paddr: physical address of the page
+ * @attrs: memory transaction attributes
+ * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits)
+ * @mmu_idx: MMU index to insert TLB entry for
+ * @size: size of the page in bytes
+ *
+ * Add an entry to this CPU's TLB (a mapping from virtual address
+ * @vaddr to physical address @paddr) with the specified memory
+ * transaction attributes. This is generally called by the target CPU
+ * specific code after it has been called through the tlb_fill()
+ * entry point and performed a successful page table walk to find
+ * the physical address and attributes for the virtual address
+ * which provoked the TLB miss.
+ *
+ * At most one entry for a given virtual address is permitted. Only a
+ * single TARGET_PAGE_SIZE region is mapped; the supplied @size is only
+ * used by tlb_flush_page.
+ */
void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
hwaddr paddr, MemTxAttrs attrs,
int prot, int mmu_idx, target_ulong size);
+/* tlb_set_page:
+ *
+ * This function is equivalent to calling tlb_set_page_with_attrs()
+ * with an @attrs argument of MEMTXATTRS_UNSPECIFIED. It's provided
+ * as a convenience for CPUs which don't use memory transaction attributes.
+ */
+void tlb_set_page(CPUState *cpu, target_ulong vaddr,
+ hwaddr paddr, int prot,
+ int mmu_idx, target_ulong size);
void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr);
void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx,
uintptr_t retaddr);
--
1.9.1
- [Qemu-devel] [PULL 18/36] memory: Add address_space_init_shareable(), (continued)
- [Qemu-devel] [PULL 18/36] memory: Add address_space_init_shareable(), Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 24/36] hw/arm/virt: Wire up memory region to CPUs explicitly, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 12/36] cpu: Add new asidx_from_attrs() method, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 16/36] exec.c: Use cpu_get_phys_page_attrs_debug, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 14/36] exec.c: Pass MemTxAttrs to iotlb_to_region so it uses the right AS, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 21/36] target-arm: Implement asidx_from_attrs, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 01/36] qdev: get_child_bus(): Use QOM lookup if available, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 19/36] qom/cpu: Add MemoryRegion property, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 25/36] hw/arm/virt: add secure memory region and UART, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 34/36] target-arm: Implement remaining illegal return event checks, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 10/36] exec-all.h: Document tlb_set_page_with_attrs, tlb_set_page,
Peter Maydell <=
- [Qemu-devel] [PULL 07/36] misc: zynq-xadc: Fix off-by-one, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 11/36] cpu: Add new get_phys_page_attrs_debug() method, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 15/36] exec.c: Add cpu_get_address_space(), Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 04/36] xilinx_spips: Separate the state struct into a header, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 09/36] exec.c: Allow target CPUs to define multiple AddressSpaces, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 02/36] m25p80.c: Add sst25wf080 SPI flash device, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 22/36] target-arm: Implement cpu_get_phys_page_attrs_debug, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 17/36] exec.c: Use correct AddressSpace in watch_mem_read and watch_mem_write, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 13/36] cputlb.c: Use correct address space when looking up MemoryRegionSection, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 03/36] ssi: Move ssi.h into a separate directory, Peter Maydell, 2016/01/21