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[Qemu-devel] [PATCH v2 4/6] target-arm: Implement missing EL2 TLBI opera
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH v2 4/6] target-arm: Implement missing EL2 TLBI operations |
Date: |
Fri, 14 Aug 2015 11:41:17 +0100 |
Implement the missing TLBI operations that exist only
if EL2 is implemented.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
---
target-arm/helper.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index aea8b33..77ce718 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2562,6 +2562,16 @@ static void tlbi_aa64_alle1is_write(CPUARMState *env,
const ARMCPRegInfo *ri,
}
}
+static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+ CPUState *other_cs;
+
+ CPU_FOREACH(other_cs) {
+ tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1E2, -1);
+ }
+}
+
static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
@@ -3065,10 +3075,22 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1,
.type = ARM_CP_NO_RAW, .access = PL2_W,
.writefn = tlbi_aa64_vae2_write },
+ { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5,
+ .access = PL2_W, .type = ARM_CP_NO_RAW,
+ .writefn = tlbi_aa64_vae2_write },
+ { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0,
+ .access = PL2_W, .type = ARM_CP_NO_RAW,
+ .writefn = tlbi_aa64_alle2is_write },
{ .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1,
.type = ARM_CP_NO_RAW, .access = PL2_W,
.writefn = tlbi_aa64_vae2is_write },
+ { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5,
+ .access = PL2_W, .type = ARM_CP_NO_RAW,
+ .writefn = tlbi_aa64_vae2is_write },
#ifndef CONFIG_USER_ONLY
{ .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
--
1.9.1
- [Qemu-devel] [PATCH v2 0/6] flush TLBs for one MMUidx only, missing AArch64 TLB ops, Peter Maydell, 2015/08/14
- [Qemu-devel] [PATCH v2 6/6] target-arm: Implement AArch64 TLBI operations on IPAs, Peter Maydell, 2015/08/14
- [Qemu-devel] [PATCH v2 4/6] target-arm: Implement missing EL2 TLBI operations,
Peter Maydell <=
- [Qemu-devel] [PATCH v2 5/6] target-arm: Implement missing EL3 TLB invalidate operations, Peter Maydell, 2015/08/14
- [Qemu-devel] [PATCH v2 2/6] target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric order, Peter Maydell, 2015/08/14
- [Qemu-devel] [PATCH v2 1/6] cputlb: Add functions for flushing TLB for a single MMU index, Peter Maydell, 2015/08/14
- [Qemu-devel] [PATCH v2 3/6] target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must touch, Peter Maydell, 2015/08/14