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[Qemu-devel] [PATCH v2 2/6] target-arm: Move TLBI ALLE1/ALLE1IS definiti
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH v2 2/6] target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric order |
Date: |
Fri, 14 Aug 2015 11:41:15 +0100 |
Move the two regdefs for TLBI ALLE1 and TLBI ALLE1IS down so that the
whole set of AArch64 TLBI regdefs is arranged in numeric order.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
---
target-arm/helper.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 1568aa6..2ca8839 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2672,14 +2672,6 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
.access = PL1_W, .type = ARM_CP_NOP },
/* TLBI operations */
- { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64,
- .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,
- .access = PL2_W, .type = ARM_CP_NO_RAW,
- .writefn = tlbiall_write },
- { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64,
- .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
- .access = PL2_W, .type = ARM_CP_NO_RAW,
- .writefn = tlbiall_is_write },
{ .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
.access = PL1_W, .type = ARM_CP_NO_RAW,
@@ -2728,6 +2720,14 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
.access = PL1_W, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_vaa_write },
+ { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
+ .access = PL2_W, .type = ARM_CP_NO_RAW,
+ .writefn = tlbiall_is_write },
+ { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,
+ .access = PL2_W, .type = ARM_CP_NO_RAW,
+ .writefn = tlbiall_write },
#ifndef CONFIG_USER_ONLY
/* 64 bit address translation operations */
{ .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
--
1.9.1
- [Qemu-devel] [PATCH v2 0/6] flush TLBs for one MMUidx only, missing AArch64 TLB ops, Peter Maydell, 2015/08/14
- [Qemu-devel] [PATCH v2 6/6] target-arm: Implement AArch64 TLBI operations on IPAs, Peter Maydell, 2015/08/14
- [Qemu-devel] [PATCH v2 4/6] target-arm: Implement missing EL2 TLBI operations, Peter Maydell, 2015/08/14
- [Qemu-devel] [PATCH v2 5/6] target-arm: Implement missing EL3 TLB invalidate operations, Peter Maydell, 2015/08/14
- [Qemu-devel] [PATCH v2 2/6] target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric order,
Peter Maydell <=
- [Qemu-devel] [PATCH v2 1/6] cputlb: Add functions for flushing TLB for a single MMU index, Peter Maydell, 2015/08/14
- [Qemu-devel] [PATCH v2 3/6] target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must touch, Peter Maydell, 2015/08/14