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Re: [Qemu-devel] [PATCH 05/14] target-i386: Enable control registers for

From: Paolo Bonzini
Subject: Re: [Qemu-devel] [PATCH 05/14] target-i386: Enable control registers for MPX
Date: Thu, 9 Jul 2015 15:12:43 +0200
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.0.1

On 09/07/2015 10:17, Richard Henderson wrote:
> +    /* ??? Vol 1, 16.5.6 Intel MPX and SMM says that IA32_BNDCFGS
> +       is saved at offset 7ED0.  Vol 3,, Table 32-2, has
> +       7EA0-7ED7 as "reserved".  What's this, and what's really
> +       supposed to happen?  */
>      x86_stq_phys(cs, sm_state + 0x7ed0, env->efer);

The format that QEMU (and KVM) are using is based on AMD's format for
the state save area.  In my copy of the AMD manual this is Table 10-1.

Reserved areas in there are 0xfef0-0xfefb and 0xff04-0xff1f.

I definitely should update KVM to save/restore BNDCFGS.  Thanks for the
heads up!


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