Re: [Qemu-devel] [RFC] Cortex-M different revisions

[Peter Maydell]

On 21 June 2015 at 15:42, Liviu Ionescu <address@hidden> wrote:
>
>> On 21 Jun 2015, at 17:09, Peter Maydell <address@hidden> wrote:
>>
>> Non-buggy guest code should not care whether
>> it is running on an r2p1 or an r2p0,
>
> probably not, but code developed on an emulated r2 might
> very well break on a physical r0.

There's lots of code that will run on QEMU but break on
real hardware. Emulation is not a substitute for testing
on the real thing.

> I was considering to differentiate them only by cpu->midr, this should be 
> easy.
>
> later, when implementing accurate exception handling, I would need
> just to test the midr bits; I'm not sure it is worth to define
> properties for these things alone.

If you want to emulate them then please use properties. Tagging
things off the MIDR is not something we do for any other
CPU property.

>> Do you have real-world guest code that breaks?
>
> yes, early M3 cores (for example the venerable STM32F1xx devices)
> have such issues that need to be addressed, usually at RTOS level,
> otherwise faults are raised.
>
> I cannot confirm (because it was quite a while ago when I had to
> deal with these issues) that it is possible to write code that works
> an all versions without checking the actual version and acting
> differently.

It should be -- just write to the architecture's specifications,
not to the variations between specific revisions.

-- PMM