[Qemu-devel] [RFC] Cortex-M different revisions

[Liviu Ionescu]

while studying the details of cortex-m cores, I ran into the many differences 
between existing revisions, especially for cortex-m3, which are numerous and 
some significative, like stack alignment. for example for m3, the changes from 
r0p0 to r1p0/r1p1 are one full page of details, like "        • the NVIC 
Configuration Control register includes the STKALIGN bit,    • r1p1 includes 
the new AUXFAULT (Auxiliary Fault) status register...", changes from r2p0 to 
r2p1 include "     • The Vector Table Offset Register (VTOR) has been increased 
by two bits to enable more flexible placement of the vector table. ...", etc

at first sight these differences would require special care when implementing 
an accurate emulation.

for this I'm considering extending the naming scheme for cortex-m cores, to 
include the revision, like "cortex-m3-r2p1", which will define the fields in 
CPUID correctly.

as per Joseph Yiu (The Definitive Guide to ARM Cortex-M3 and M4, Third edition, 
p. 765), "The revisions for the Cortex-M3 processor include: r0p0, r1p0, r1p1, 
r2p0, and r2p1. The revisions for the Cortex-M4 processor include: r0p0, r0p1."


any comments? 

Liviu