[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v6 09/10] target-arm: Add IRQ and FIQ routing to EL2
From: |
Edgar E. Iglesias |
Subject: |
[Qemu-devel] [PATCH v6 09/10] target-arm: Add IRQ and FIQ routing to EL2 and 3 |
Date: |
Sat, 13 Sep 2014 14:29:23 +1000 |
From: "Edgar E. Iglesias" <address@hidden>
Reviewed-by: Greg Bellows <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
target-arm/cpu.h | 12 ++++++++++++
target-arm/helper.c | 14 ++++++++++++++
2 files changed, 26 insertions(+)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index c24af40..a5123f8 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -1178,6 +1178,12 @@ static inline bool arm_excp_unmasked(CPUState *cs,
unsigned int excp_idx)
CPUARMState *env = cs->env_ptr;
unsigned int cur_el = arm_current_pl(env);
unsigned int target_el = arm_excp_target_el(cs, excp_idx);
+ /* FIXME: Use actual secure state. */
+ bool secure = false;
+ /* Interrupts can only be hypervised and routed to
+ * EL2 if we are in NS EL0/1.
+ */
+ bool irq_can_hyp = !secure && cur_el < 2 && target_el == 2;
/* Don't take exceptions if they target a lower EL. */
if (cur_el > target_el) {
@@ -1186,8 +1192,14 @@ static inline bool arm_excp_unmasked(CPUState *cs,
unsigned int excp_idx)
switch (excp_idx) {
case EXCP_FIQ:
+ if (irq_can_hyp && (env->cp15.hcr_el2 & HCR_FMO)) {
+ return true;
+ }
return !(env->daif & PSTATE_F);
case EXCP_IRQ:
+ if (irq_can_hyp && (env->cp15.hcr_el2 & HCR_IMO)) {
+ return true;
+ }
return !(env->daif & PSTATE_I)
&& (!IS_M(env) || env->regs[15] < 0xfffffff0);
default:
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 719c95d..3a9d1fc 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3683,6 +3683,20 @@ unsigned int arm_excp_target_el(CPUState *cs, unsigned
int excp_idx)
target_el = 2;
}
break;
+ case EXCP_FIQ:
+ case EXCP_IRQ:
+ {
+ const uint64_t hcr_mask = excp_idx == EXCP_FIQ ? HCR_FMO : HCR_IMO;
+ const uint32_t scr_mask = excp_idx == EXCP_FIQ ? SCR_FIQ : SCR_IRQ;
+
+ if (!secure && (env->cp15.hcr_el2 & hcr_mask)) {
+ target_el = 2;
+ }
+ if (env->cp15.scr_el3 & scr_mask) {
+ target_el = 3;
+ }
+ break;
+ }
}
return target_el;
}
--
1.9.1
- Re: [Qemu-devel] [PATCH v6 07/10] target-arm: A64: Emulate the HVC insn, (continued)
- [Qemu-devel] [PATCH v6 08/10] target-arm: A64: Emulate the SMC insn, Edgar E. Iglesias, 2014/09/13
- Re: [Qemu-devel] [PATCH v6 08/10] target-arm: A64: Emulate the SMC insn, Greg Bellows, 2014/09/17
- Re: [Qemu-devel] [PATCH v6 08/10] target-arm: A64: Emulate the SMC insn, Peter Maydell, 2014/09/25
- Re: [Qemu-devel] [PATCH v6 08/10] target-arm: A64: Emulate the SMC insn, Edgar E. Iglesias, 2014/09/25
- Re: [Qemu-devel] [PATCH v6 08/10] target-arm: A64: Emulate the SMC insn, Peter Maydell, 2014/09/25
- Re: [Qemu-devel] [PATCH v6 08/10] target-arm: A64: Emulate the SMC insn, Edgar E. Iglesias, 2014/09/25
- Re: [Qemu-devel] [PATCH v6 08/10] target-arm: A64: Emulate the SMC insn, Peter Maydell, 2014/09/25
- Re: [Qemu-devel] [PATCH v6 08/10] target-arm: A64: Emulate the SMC insn, Edgar E. Iglesias, 2014/09/25
- Re: [Qemu-devel] [PATCH v6 08/10] target-arm: A64: Emulate the SMC insn, Edgar E. Iglesias, 2014/09/26
[Qemu-devel] [PATCH v6 09/10] target-arm: Add IRQ and FIQ routing to EL2 and 3,
Edgar E. Iglesias <=
[Qemu-devel] [PATCH v6 10/10] target-arm: Add support for VIRQ and VFIQ, Edgar E. Iglesias, 2014/09/13