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[Qemu-devel] [PULL 09/16] hw/intc/arm_gic: honor target mask in gic_upda
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 09/16] hw/intc/arm_gic: honor target mask in gic_update() |
Date: |
Fri, 29 Aug 2014 15:37:21 +0100 |
From: Sergey Fedorov <address@hidden>
Take IRQ target mask into account when determining the highest priority
pending interrupt.
Signed-off-by: Sergey Fedorov <address@hidden>
Acked-by: Christoffer Dall <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/intc/arm_gic.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 55019c9..db9110c 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -66,7 +66,8 @@ void gic_update(GICState *s)
best_prio = 0x100;
best_irq = 1023;
for (irq = 0; irq < s->num_irq; irq++) {
- if (GIC_TEST_ENABLED(irq, cm) && gic_test_pending(s, irq, cm)) {
+ if (GIC_TEST_ENABLED(irq, cm) && gic_test_pending(s, irq, cm) &&
+ (irq < GIC_INTERNAL || GIC_TARGET(irq) & cm)) {
if (GIC_GET_PRIORITY(irq, cpu) < best_prio) {
best_prio = GIC_GET_PRIORITY(irq, cpu);
best_irq = irq;
--
1.9.1
- [Qemu-devel] [PULL 00/16] target-arm queue, Peter Maydell, 2014/08/29
- [Qemu-devel] [PULL 14/16] target-arm: Implement pmccntr_sync function, Peter Maydell, 2014/08/29
- [Qemu-devel] [PULL 13/16] target-arm: Add arm_ccnt_enabled function, Peter Maydell, 2014/08/29
- [Qemu-devel] [PULL 16/16] target-arm: Implement pmccfiltr_write function, Peter Maydell, 2014/08/29
- [Qemu-devel] [PULL 12/16] target-arm: Implement PMCCNTR_EL0 and related registers, Peter Maydell, 2014/08/29
- [Qemu-devel] [PULL 11/16] arm: Implement PMCCNTR 32b read-modify-write, Peter Maydell, 2014/08/29
- [Qemu-devel] [PULL 01/16] disas/libvixl: Update to upstream VIXL 1.5, Peter Maydell, 2014/08/29
- [Qemu-devel] [PULL 09/16] hw/intc/arm_gic: honor target mask in gic_update(),
Peter Maydell <=
- [Qemu-devel] [PULL 02/16] target-arm: Fix regression that disabled VFP for ARMv5 CPUs, Peter Maydell, 2014/08/29
- [Qemu-devel] [PULL 03/16] target-arm: Correct Cortex-A57 ISAR5 and AA64ISAR0 ID register values, Peter Maydell, 2014/08/29
- [Qemu-devel] [PULL 07/16] arm_gic: Use GIC_NR_SGIS constant, Peter Maydell, 2014/08/29
- [Qemu-devel] [PULL 04/16] arm_gic: Fix read of GICD_ICFGR, Peter Maydell, 2014/08/29
- [Qemu-devel] [PULL 10/16] target-arm: Make the ARM PMCCNTR register 64-bit, Peter Maydell, 2014/08/29
- [Qemu-devel] [PULL 08/16] aarch64: raise max_cpus to 8, Peter Maydell, 2014/08/29
- [Qemu-devel] [PULL 05/16] arm_gic: GICD_ICFGR: Write model only for pre v1 GICs, Peter Maydell, 2014/08/29
- [Qemu-devel] [PULL 15/16] target-arm: Remove old code and replace with new functions, Peter Maydell, 2014/08/29
- [Qemu-devel] [PULL 06/16] arm_gic: Do not force PPIs to edge-triggered mode, Peter Maydell, 2014/08/29
- Re: [Qemu-devel] [PULL 00/16] target-arm queue, Peter Maydell, 2014/08/29