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[Qemu-devel] [PULL 13/16] target-arm: Add arm_ccnt_enabled function
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 13/16] target-arm: Add arm_ccnt_enabled function |
Date: |
Fri, 29 Aug 2014 15:37:25 +0100 |
From: Alistair Francis <address@hidden>
Include a helper function to determine if the CCNT counter
is enabled.
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
[ PC changes
* Remove EL based checks
]
Signed-off-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/helper.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 13507f7..e6c82ab 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -548,6 +548,18 @@ static CPAccessResult pmreg_access(CPUARMState *env, const
ARMCPRegInfo *ri)
}
#ifndef CONFIG_USER_ONLY
+
+static inline bool arm_ccnt_enabled(CPUARMState *env)
+{
+ /* This does not support checking PMCCFILTR_EL0 register */
+
+ if (!(env->cp15.c9_pmcr & PMCRE)) {
+ return false;
+ }
+
+ return true;
+}
+
static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
--
1.9.1
- [Qemu-devel] [PULL 00/16] target-arm queue, Peter Maydell, 2014/08/29
- [Qemu-devel] [PULL 14/16] target-arm: Implement pmccntr_sync function, Peter Maydell, 2014/08/29
- [Qemu-devel] [PULL 13/16] target-arm: Add arm_ccnt_enabled function,
Peter Maydell <=
- [Qemu-devel] [PULL 16/16] target-arm: Implement pmccfiltr_write function, Peter Maydell, 2014/08/29
- [Qemu-devel] [PULL 12/16] target-arm: Implement PMCCNTR_EL0 and related registers, Peter Maydell, 2014/08/29
- [Qemu-devel] [PULL 11/16] arm: Implement PMCCNTR 32b read-modify-write, Peter Maydell, 2014/08/29
- [Qemu-devel] [PULL 01/16] disas/libvixl: Update to upstream VIXL 1.5, Peter Maydell, 2014/08/29
- [Qemu-devel] [PULL 09/16] hw/intc/arm_gic: honor target mask in gic_update(), Peter Maydell, 2014/08/29
- [Qemu-devel] [PULL 02/16] target-arm: Fix regression that disabled VFP for ARMv5 CPUs, Peter Maydell, 2014/08/29
- [Qemu-devel] [PULL 03/16] target-arm: Correct Cortex-A57 ISAR5 and AA64ISAR0 ID register values, Peter Maydell, 2014/08/29
- [Qemu-devel] [PULL 07/16] arm_gic: Use GIC_NR_SGIS constant, Peter Maydell, 2014/08/29
- [Qemu-devel] [PULL 04/16] arm_gic: Fix read of GICD_ICFGR, Peter Maydell, 2014/08/29
- [Qemu-devel] [PULL 10/16] target-arm: Make the ARM PMCCNTR register 64-bit, Peter Maydell, 2014/08/29