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[Qemu-devel] [PATCH 16/20] target-i386: unify reserved bits and NX bit c
From: |
Paolo Bonzini |
Subject: |
[Qemu-devel] [PATCH 16/20] target-i386: unify reserved bits and NX bit check |
Date: |
Tue, 27 May 2014 15:23:14 +0200 |
Signed-off-by: Paolo Bonzini <address@hidden>
---
target-i386/helper.c | 16 ++++------------
1 file changed, 4 insertions(+), 12 deletions(-)
diff --git a/target-i386/helper.c b/target-i386/helper.c
index 153a91b..a2e8bd1 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -549,6 +549,10 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr,
goto do_mapping;
}
+ if (!(env->efer & MSR_EFER_NXE)) {
+ rsvd_mask |= PG_NX_MASK;
+ }
+
if (env->cr[4] & CR4_PAE_MASK) {
uint64_t pde, pdpe;
target_ulong pdpe_addr;
@@ -575,9 +579,6 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr,
if (pml4e & (rsvd_mask | PG_PSE_MASK)) {
goto do_fault_rsvd;
}
- if (!(env->efer & MSR_EFER_NXE) && (pml4e & PG_NX_MASK)) {
- goto do_fault_rsvd;
- }
if (!(pml4e & PG_ACCESSED_MASK)) {
pml4e |= PG_ACCESSED_MASK;
stl_phys_notdirty(cs->as, pml4e_addr, pml4e);
@@ -592,9 +593,6 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr,
if (pdpe & rsvd_mask) {
goto do_fault_rsvd;
}
- if (!(env->efer & MSR_EFER_NXE) && (pdpe & PG_NX_MASK)) {
- goto do_fault_rsvd;
- }
ptep &= pdpe ^ PG_NX_MASK;
if (!(pdpe & PG_ACCESSED_MASK)) {
pdpe |= PG_ACCESSED_MASK;
@@ -633,9 +631,6 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr,
if (pde & rsvd_mask) {
goto do_fault_rsvd;
}
- if (!(env->efer & MSR_EFER_NXE) && (pde & PG_NX_MASK)) {
- goto do_fault_rsvd;
- }
ptep &= pde ^ PG_NX_MASK;
if (pde & PG_PSE_MASK) {
/* 2 MB page */
@@ -658,9 +653,6 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr,
if (pte & rsvd_mask) {
goto do_fault_rsvd;
}
- if (!(env->efer & MSR_EFER_NXE) && (pte & PG_NX_MASK)) {
- goto do_fault_rsvd;
- }
/* combine pde and pte nx, user and rw protections */
ptep &= pte ^ PG_NX_MASK;
page_size = 4096;
--
1.8.3.1
- [Qemu-devel] [PATCH 06/20] target-i386: commonize checks for 2MB and 4KB pages, (continued)
- [Qemu-devel] [PATCH 06/20] target-i386: commonize checks for 2MB and 4KB pages, Paolo Bonzini, 2014/05/27
- [Qemu-devel] [PATCH 07/20] target-i386: commonize checks for 4MB and 4KB pages, Paolo Bonzini, 2014/05/27
- [Qemu-devel] [PATCH 08/20] target-i386: commonize checks for PAE and non-PAE, Paolo Bonzini, 2014/05/27
- [Qemu-devel] [PATCH 10/20] target-i386: introduce do_check_protect label, Paolo Bonzini, 2014/05/27
- [Qemu-devel] [PATCH 09/20] target-i386: tweak handling of PG_NX_MASK, Paolo Bonzini, 2014/05/27
- [Qemu-devel] [PATCH 12/20] target-i386: set correct error code for reserved bit access, Paolo Bonzini, 2014/05/27
- [Qemu-devel] [PATCH 13/20] target-i386: test reserved PS bit on PML4Es, Paolo Bonzini, 2014/05/27
- [Qemu-devel] [PATCH 11/20] target-i386: introduce support for 1 GB pages, Paolo Bonzini, 2014/05/27
- [Qemu-devel] [PATCH 14/20] target-i386: raise page fault for reserved physical address bits, Paolo Bonzini, 2014/05/27
- [Qemu-devel] [PATCH 15/20] target-i386: simplify pte/vaddr calculation, Paolo Bonzini, 2014/05/27
- [Qemu-devel] [PATCH 16/20] target-i386: unify reserved bits and NX bit check,
Paolo Bonzini <=
- [Qemu-devel] [PATCH 17/20] target-i386: raise page fault for reserved bits in large pages, Paolo Bonzini, 2014/05/27
- [Qemu-devel] [PATCH 18/20] target-i386: support long addresses for 4MB pages (PSE-36), Paolo Bonzini, 2014/05/27
- [Qemu-devel] [PATCH 19/20] target-i386: fix protection bits in the TLB for SMEP, Paolo Bonzini, 2014/05/27
- [Qemu-devel] [PATCH 20/20] target-i386: cleanup x86_cpu_get_phys_page_debug, Paolo Bonzini, 2014/05/27