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[Qemu-devel] [PULL 14/51] target-arm: Implement AArch64 views of fault s
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 14/51] target-arm: Implement AArch64 views of fault status and data registers |
Date: |
Thu, 17 Apr 2014 11:33:29 +0100 |
From: Rob Herring <address@hidden>
Implement AArch64 views of ESR_EL1 and FAR_EL1, and make the 32 bit
DFSR, DFAR, IFAR share state with them as architecturally specified.
The IFSR doesn't share state with any AArch64 register visible at EL1,
so just rename the state field without widening it to 64 bits.
Signed-off-by: Rob Herring <address@hidden>
[PMM: Minor tweaks; fix some bugs involving inconsistencies between
use of offsetof() or offsetoflow32() and struct field width]
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
---
target-arm/cpu.c | 2 +-
target-arm/cpu.h | 7 +++----
target-arm/helper.c | 38 +++++++++++++++++++++++++-------------
3 files changed, 29 insertions(+), 18 deletions(-)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index d62b792..a3c7492 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -425,7 +425,7 @@ static void arm1026_initfn(Object *obj)
ARMCPRegInfo ifar = {
.name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
.access = PL1_RW,
- .fieldoffset = offsetof(CPUARMState, cp15.c6_insn),
+ .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el1),
.resetvalue = 0
};
define_one_arm_cp_reg(cpu, &ifar);
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 42fa7db..4ca75cd 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -181,11 +181,10 @@ typedef struct CPUARMState {
MPU write buffer control. */
uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */
uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */
- uint32_t c5_insn; /* Fault status registers. */
- uint32_t c5_data;
+ uint32_t ifsr_el2; /* Fault status registers. */
+ uint64_t esr_el1;
uint32_t c6_region[8]; /* MPU base/size registers. */
- uint32_t c6_insn; /* Fault address registers. */
- uint32_t c6_data;
+ uint64_t far_el1; /* Fault address registers. */
uint32_t c7_par; /* Translation result. */
uint32_t c7_par_hi; /* Translation result, high 32 bits */
uint32_t c9_insn; /* Cache lockdown registers. */
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 289a5c0..5f6233b 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -475,7 +475,8 @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
{ .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
.access = PL0_W, .type = ARM_CP_NOP },
{ .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
- .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_insn),
+ .access = PL1_RW,
+ .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el1),
.resetvalue = 0, },
/* Watchpoint Fault Address Register : should actually only be present
* for 1136, 1176, 11MPCore.
@@ -1414,11 +1415,16 @@ static void vmsa_ttbr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
static const ARMCPRegInfo vmsa_cp_reginfo[] = {
{ .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
- .access = PL1_RW,
- .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
+ .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
+ .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el1),
+ .resetfn = arm_cp_reset_ignore, },
{ .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
.access = PL1_RW,
- .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
+ .fieldoffset = offsetof(CPUARMState, cp15.ifsr_el2), .resetvalue = 0, },
+ { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0,
+ .access = PL1_RW,
+ .fieldoffset = offsetof(CPUARMState, cp15.esr_el1), .resetvalue = 0, },
{ .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1),
@@ -1436,8 +1442,10 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
.access = PL1_RW, .type = ARM_CP_NO_MIGRATE, .writefn = vmsa_ttbcr_write,
.resetfn = arm_cp_reset_ignore, .raw_writefn = vmsa_ttbcr_raw_write,
.fieldoffset = offsetoflow32(CPUARMState, cp15.c2_control) },
- { .name = "DFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
- .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_data),
+ /* 64-bit FAR; this entry also gives us the AArch32 DFAR */
+ { .name = "FAR_EL1", .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
+ .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el1),
.resetvalue = 0, },
REGINFO_SENTINEL
};
@@ -1477,7 +1485,8 @@ static void omap_cachemaint_write(CPUARMState *env, const
ARMCPRegInfo *ri,
static const ARMCPRegInfo omap_cp_reginfo[] = {
{ .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
.opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type =
ARM_CP_OVERRIDE,
- .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
+ .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el1),
+ .resetvalue = 0, },
{ .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
.access = PL1_RW, .type = ARM_CP_NOP },
{ .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
@@ -3087,20 +3096,23 @@ void arm_cpu_do_interrupt(CPUState *cs)
env->exception.fsr = 2;
/* Fall through to prefetch abort. */
case EXCP_PREFETCH_ABORT:
- env->cp15.c5_insn = env->exception.fsr;
- env->cp15.c6_insn = env->exception.vaddress;
+ env->cp15.ifsr_el2 = env->exception.fsr;
+ env->cp15.far_el1 = deposit64(env->cp15.far_el1, 32, 32,
+ env->exception.vaddress);
qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n",
- env->cp15.c5_insn, env->cp15.c6_insn);
+ env->cp15.ifsr_el2, (uint32_t)env->exception.vaddress);
new_mode = ARM_CPU_MODE_ABT;
addr = 0x0c;
mask = CPSR_A | CPSR_I;
offset = 4;
break;
case EXCP_DATA_ABORT:
- env->cp15.c5_data = env->exception.fsr;
- env->cp15.c6_data = env->exception.vaddress;
+ env->cp15.esr_el1 = env->exception.fsr;
+ env->cp15.far_el1 = deposit64(env->cp15.far_el1, 0, 32,
+ env->exception.vaddress);
qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",
- env->cp15.c5_data, env->cp15.c6_data);
+ (uint32_t)env->cp15.esr_el1,
+ (uint32_t)env->exception.vaddress);
new_mode = ARM_CPU_MODE_ABT;
addr = 0x10;
mask = CPSR_A | CPSR_I;
--
1.9.1
- [Qemu-devel] [PULL 25/51] target-arm: Implement ISR_EL1 register, (continued)
- [Qemu-devel] [PULL 25/51] target-arm: Implement ISR_EL1 register, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 18/51] target-arm: Move arm_log_exception() into internals.h, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 21/51] target-arm: Add Cortex-A57 processor, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 19/51] target-arm: Implement AArch64 EL1 exception handling, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 22/51] target-arm: Implement AArch64 views of AArch32 ID registers, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 17/51] target-arm: Implement AArch64 SPSR_EL1, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 15/51] target-arm: Add AArch64 ELR_EL1 register., Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 16/51] target-arm: Implement SP_EL0, SP_EL1, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 23/51] target-arm: Implement AArch64 view of CONTEXTIDR, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 13/51] target-arm: Use dedicated CPU state fields for ARM946 access bit registers, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 14/51] target-arm: Implement AArch64 views of fault status and data registers,
Peter Maydell <=
- [Qemu-devel] [PULL 09/51] target-arm: Fix VFP enables for AArch32 EL0 under AArch64 EL1, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 11/51] target-arm: Don't mention PMU in debug feature register, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 12/51] target-arm: A64: Implement DC ZVA, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 08/51] target-arm: A64: Add assertion that FP access was checked, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 06/51] target-arm: Provide syndrome information for MMU faults, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 10/51] target-arm: Add v8 mmu translation support, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 05/51] target-arm: Add support for generating exceptions with syndrome information, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 02/51] target-arm: Implement AArch64 DAIF system register, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 03/51] target-arm: Define exception record for AArch64 exceptions, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 07/51] target-arm: A64: Correctly fault FP/Neon if CPACR.FPEN set, Peter Maydell, 2014/04/17