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[Qemu-devel] [PULL 25/51] target-arm: Implement ISR_EL1 register
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 25/51] target-arm: Implement ISR_EL1 register |
Date: |
Thu, 17 Apr 2014 11:33:40 +0100 |
Implement the ISR_EL1 register. This is actually present in
ARMv7 as well but was previously unimplemented. It is a
read-only register that indicates whether interrupts are
currently pending.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
---
target-arm/helper.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 32af1df..825c8c9 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -665,6 +665,21 @@ static void csselr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
env->cp15.c0_cssel = value & 0xf;
}
+static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+ CPUState *cs = ENV_GET_CPU(env);
+ uint64_t ret = 0;
+
+ if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
+ ret |= CPSR_I;
+ }
+ if (cs->interrupt_request & CPU_INTERRUPT_FIQ) {
+ ret |= CPSR_F;
+ }
+ /* External aborts are not possible in QEMU so A bit is always clear */
+ return ret;
+}
+
static const ARMCPRegInfo v7_cp_reginfo[] = {
/* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
* debug components
@@ -782,6 +797,9 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
.cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW,
.fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el1),
.resetfn = arm_cp_reset_ignore },
+ { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,
+ .type = ARM_CP_NO_MIGRATE, .access = PL1_R, .readfn = isr_read },
REGINFO_SENTINEL
};
--
1.9.1
- [Qemu-devel] [PULL 32/51] target-arm: Implement Cortex-A57 implementation-defined system registers, (continued)
- [Qemu-devel] [PULL 32/51] target-arm: Implement Cortex-A57 implementation-defined system registers, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 31/51] target-arm: Implement RVBAR register, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 29/51] target-arm: Implement auxiliary fault status registers, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 30/51] target-arm: Implement AArch64 address translation operations, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 40/51] allwinner-a10-pic: fix behaviour of pending register, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 27/51] target-arm: Don't expose wildcard ID register definitions for ARMv8, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 28/51] target-arm: Replace wildcarded cpreg definitions with precise ones for ARMv8, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 26/51] target-arm: Remove THUMB2EE feature from AArch64 'any' CPU, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 24/51] target-arm: Implement AArch64 view of ACTLR, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 20/51] target-arm: Implement ARMv8 MVFR registers, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 25/51] target-arm: Implement ISR_EL1 register,
Peter Maydell <=
- [Qemu-devel] [PULL 18/51] target-arm: Move arm_log_exception() into internals.h, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 21/51] target-arm: Add Cortex-A57 processor, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 19/51] target-arm: Implement AArch64 EL1 exception handling, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 22/51] target-arm: Implement AArch64 views of AArch32 ID registers, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 17/51] target-arm: Implement AArch64 SPSR_EL1, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 15/51] target-arm: Add AArch64 ELR_EL1 register., Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 16/51] target-arm: Implement SP_EL0, SP_EL1, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 23/51] target-arm: Implement AArch64 view of CONTEXTIDR, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 13/51] target-arm: Use dedicated CPU state fields for ARM946 access bit registers, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 14/51] target-arm: Implement AArch64 views of fault status and data registers, Peter Maydell, 2014/04/17