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[Qemu-devel] [PULL 08/52] target-arm: A64: implement SVC, BRK
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 08/52] target-arm: A64: implement SVC, BRK |
Date: |
Mon, 6 Jan 2014 11:30:13 +0000 |
From: Alexander Graf <address@hidden>
Add decoding for the exception generating instructions, and implement
SVC (syscalls) and BRK (software breakpoint).
Signed-off-by: Alexander Graf <address@hidden>
Signed-off-by: Alex Bennée <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target-arm/translate-a64.c | 51 ++++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 49 insertions(+), 2 deletions(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 3a9ffdf..9ca6460 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -808,10 +808,57 @@ static void disas_system(DisasContext *s, uint32_t insn)
}
}
-/* Exception generation */
+/* C3.2.3 Exception generation
+ *
+ * 31 24 23 21 20 5 4 2 1 0
+ * +-----------------+-----+------------------------+-----+----+
+ * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
+ * +-----------------------+------------------------+----------+
+ */
static void disas_exc(DisasContext *s, uint32_t insn)
{
- unsupported_encoding(s, insn);
+ int opc = extract32(insn, 21, 3);
+ int op2_ll = extract32(insn, 0, 5);
+
+ switch (opc) {
+ case 0:
+ /* SVC, HVC, SMC; since we don't support the Virtualization
+ * or TrustZone extensions these all UNDEF except SVC.
+ */
+ if (op2_ll != 1) {
+ unallocated_encoding(s);
+ break;
+ }
+ gen_exception_insn(s, 0, EXCP_SWI);
+ break;
+ case 1:
+ if (op2_ll != 0) {
+ unallocated_encoding(s);
+ break;
+ }
+ /* BRK */
+ gen_exception_insn(s, 0, EXCP_BKPT);
+ break;
+ case 2:
+ if (op2_ll != 0) {
+ unallocated_encoding(s);
+ break;
+ }
+ /* HLT */
+ unsupported_encoding(s, insn);
+ break;
+ case 5:
+ if (op2_ll < 1 || op2_ll > 3) {
+ unallocated_encoding(s);
+ break;
+ }
+ /* DCPS1, DCPS2, DCPS3 */
+ unsupported_encoding(s, insn);
+ break;
+ default:
+ unallocated_encoding(s);
+ break;
+ }
}
/* C3.2.7 Unconditional branch (register)
--
1.8.5
- [Qemu-devel] [PULL 31/52] target-arm: A64: Add fmov (scalar, immediate) instruction, (continued)
- [Qemu-devel] [PULL 31/52] target-arm: A64: Add fmov (scalar, immediate) instruction, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 42/52] char/cadence_uart: Remove TX timer & add TX FIFO state, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 30/52] target-arm: A64: Add "Floating-point data-processing (3 source)" insns, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 26/52] target-arm: A64: Add support for dumping AArch64 VFP register state, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 28/52] target-arm: Use VFP_BINOP macro for min, max, minnum, maxnum, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 27/52] target-arm: A64: Fix vector register access on bigendian hosts, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 32/52] target-arm: A64: Add support for floating point compare, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 24/52] .travis.yml: Add aarch64-* targets, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 25/52] default-configs: Add config for aarch64-linux-user, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 21/52] target-arm: A64: support for ld/st/cl exclusive, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 08/52] target-arm: A64: implement SVC, BRK,
Peter Maydell <=
- [Qemu-devel] [PULL 19/52] target-arm: aarch64: add support for ld lit, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 07/52] target-arm: A64: add support for 3 src data proc insns, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 29/52] target-arm: A64: Add "Floating-point data-processing (2 source)" insns, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 20/52] target-arm: Widen exclusive-access support struct fields to 64 bits, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 03/52] target-arm: A64: add support for ld/st with reg offset, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 04/52] target-arm: A64: add support for ld/st with index, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 09/52] target-arm: A64: Add decoder skeleton for FP instructions, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 22/52] linux-user: AArch64: define TARGET_CLONE_BACKWARDS, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 13/52] target-arm: Remove ARMCPU/CPUARMState from cpregs APIs used by decoder, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 01/52] target-arm: A64: add support for ld/st pair, Peter Maydell, 2014/01/06