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[Qemu-devel] [PATCH v3 20/29] tcg-aarch64: Improve tcg_out_movi
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v3 20/29] tcg-aarch64: Improve tcg_out_movi |
Date: |
Mon, 2 Sep 2013 10:54:54 -0700 |
Handle small positive and negative numbers early. Check for logical
immediates. Check if using MOVN for the first set helps.
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/aarch64/tcg-target.c | 61 +++++++++++++++++++++++++++++++++++++++++-------
1 file changed, 53 insertions(+), 8 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index 59e5026..54f5ce8 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -534,20 +534,65 @@ static inline void tcg_out_movr_sp(TCGContext *s, bool
ext,
}
static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
- tcg_target_long value)
+ tcg_target_long svalue)
{
- AArch64Insn insn = INSN_MOVZ;
+ tcg_target_ulong value = svalue;
+ AArch64Insn insn;
+ bool ext = true;
+ int wantinv, shift;
if (type == TCG_TYPE_I32) {
- value = (uint32_t)value;
+ value = (uint32_t)svalue;
+ svalue = (int32_t)svalue;
+ ext = false;
+ } else if ((value & ~0xffffffffull) == 0) {
+ svalue = (int32_t)svalue;
+ ext = false;
+ }
+
+ /* Check small positive values. */
+ if ((value & ~0xffffull) == 0) {
+ tcg_fmt_Rd_uimm_s(s, INSN_MOVZ, 0, rd, value, 0);
+ return;
+ }
+ /* Check small negative values. */
+ if ((~svalue & 0xffffull) == 0) {
+ tcg_fmt_Rd_uimm_s(s, INSN_MOVN, ext, rd, ~svalue, 0);
+ return;
}
+ /* Check for bitfield immediates. */
+ if (is_limm(svalue)) {
+ tcg_fmt_Rdn_limm(s, INSN_ORRI, ext, rd, TCG_REG_XZR, svalue);
+ return;
+ }
+
+ /* Would it take fewer insns to begin with MOVN? */
+ insn = INSN_MOVZ;
+ wantinv = 0;
+ wantinv += (value & 0x000000000000ffffull) == 0;
+ wantinv += (value & 0x00000000ffff0000ull) == 0;
+ wantinv += (value & 0x0000ffff00000000ull) == 0;
+ wantinv += (value & 0xffff000000000000ull) == 0;
+ wantinv = -wantinv;
+ wantinv += (~value & 0x000000000000ffffull) == 0;
+ wantinv += (~value & 0x00000000ffff0000ull) == 0;
+ wantinv += (~value & 0x0000ffff00000000ull) == 0;
+ wantinv += (~value & 0xffff000000000000ull) == 0;
+ if (wantinv > 0) {
+ insn = INSN_MOVN;
+ value = ~value;
+ }
+
+ shift = ctz64(value) & (63 & -16);
+ tcg_fmt_Rd_uimm_s(s, insn, ext, rd, value >> shift, shift);
+ value &= ~(0xffffUL << shift);
- do {
- unsigned shift = ctz64(value) & (63 & -16);
- tcg_fmt_Rd_uimm_s(s, insn, shift >= 32, rd, value >> shift, shift);
+ while (value) {
+ shift = ctz64(value) & (63 & -16);
+ tcg_fmt_Rd_uimm_s(s, INSN_MOVK, ext, rd,
+ (value ^ -(wantinv > 0)) >> shift, shift);
value &= ~(0xffffUL << shift);
- insn = INSN_MOVK;
- } while (value);
+ }
}
static inline void tcg_out_ldst_r(TCGContext *s,
--
1.8.3.1
- [Qemu-devel] [PATCH v3 15/29] tcg-aarch64: Support deposit, (continued)
- [Qemu-devel] [PATCH v3 15/29] tcg-aarch64: Support deposit, Richard Henderson, 2013/09/02
- [Qemu-devel] [PATCH v3 14/29] tcg-aarch64: Support movcond, Richard Henderson, 2013/09/02
- [Qemu-devel] [PATCH v3 16/29] tcg-aarch64: Support add2, sub2, Richard Henderson, 2013/09/02
- [Qemu-devel] [PATCH v3 17/29] tcg-aarch64: Support muluh, mulsh, Richard Henderson, 2013/09/02
- [Qemu-devel] [PATCH v3 18/29] tcg-aarch64: Support div, rem, Richard Henderson, 2013/09/02
- [Qemu-devel] [PATCH v3 19/29] tcg-aarch64: Introduce tcg_fmt_Rd_uimm_s, Richard Henderson, 2013/09/02
[Qemu-devel] [PATCH v3 20/29] tcg-aarch64: Improve tcg_out_movi,
Richard Henderson <=
[Qemu-devel] [PATCH v3 21/29] tcg-aarch64: Avoid add with zero in tlb load, Richard Henderson, 2013/09/02
[Qemu-devel] [PATCH v3 23/29] tcg-aarch64: Pass return address to load/store helpers directly., Richard Henderson, 2013/09/02
[Qemu-devel] [PATCH v3 22/29] tcg-aarch64: Use adrp in tcg_out_movi, Richard Henderson, 2013/09/02
[Qemu-devel] [PATCH v3 24/29] tcg-aarch64: Use tcg_out_call for qemu_ld/st, Richard Henderson, 2013/09/02
[Qemu-devel] [PATCH v3 25/29] tcg-aarch64: Use symbolic names for branches, Richard Henderson, 2013/09/02
[Qemu-devel] [PATCH v3 27/29] tcg-aarch64: Reuse FP and LR in translated code, Richard Henderson, 2013/09/02
[Qemu-devel] [PATCH v3 26/29] tcg-aarch64: Implement tcg_register_jit, Richard Henderson, 2013/09/02
[Qemu-devel] [PATCH v3 28/29] tcg-aarch64: Introduce tcg_out_ldst_pair, Richard Henderson, 2013/09/02
[Qemu-devel] [PATCH v3 29/29] tcg-aarch64: Remove redundant CPU_TLB_ENTRY_BITS check, Richard Henderson, 2013/09/02
Re: [Qemu-devel] [PATCH v3 00/29] tcg-aarch64 improvements, Richard W.M. Jones, 2013/09/03