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[Qemu-devel] [PATCH 6/6] arm: move load and store helpers, switch to ARE
From: |
Blue Swirl |
Subject: |
[Qemu-devel] [PATCH 6/6] arm: move load and store helpers, switch to AREG0 free mode |
Date: |
Mon, 19 Mar 2012 21:57:32 +0000 |
Add an explicit CPUARMState parameter instead of relying on AREG0
and move load and store helpers to helper.c. Remove AREG0 swapping in
tlb_fill(). Remove now empty op_helper.c.
Switch to AREG0 free mode. Use cpu_ld{l,uw}_code in translation
and interrupt handling.
Signed-off-by: Blue Swirl <address@hidden>
---
Makefile.target | 4 +-
configure | 2 +-
target-arm/helper.c | 54 +++++++++++++++++++++++++++++++++---
target-arm/op_helper.c | 71 ------------------------------------------------
target-arm/translate.c | 6 ++--
5 files changed, 56 insertions(+), 81 deletions(-)
delete mode 100644 target-arm/op_helper.c
diff --git a/Makefile.target b/Makefile.target
index 37fb7ed..971b7eb 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -80,7 +80,7 @@ libobj-y = exec.o translate-all.o cpu-exec.o translate.o
libobj-y += tcg/tcg.o tcg/optimize.o
libobj-$(CONFIG_TCG_INTERPRETER) += tci.o
libobj-y += fpu/softfloat.o
-ifneq ($(TARGET_BASE_ARCH), sparc)
+ifndef CONFIG_TCG_PASS_AREG0
libobj-y += op_helper.o
endif
libobj-y += helper.o
@@ -106,7 +106,7 @@ $(libobj-y): $(GENERATED_HEADERS)
# HELPER_CFLAGS is used for all the legacy code compiled with static register
# variables
-ifneq ($(TARGET_BASE_ARCH), sparc)
+ifndef CONFIG_TCG_PASS_AREG0
op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
endif
user-exec.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
diff --git a/configure b/configure
index 8b4e3c1..fe84d61 100755
--- a/configure
+++ b/configure
@@ -3608,7 +3608,7 @@ case "$target_arch2" in
esac
case "$target_arch2" in
- sparc*)
+ sparc*|arm*)
echo "CONFIG_TCG_PASS_AREG0=y" >> $config_target_mak
;;
esac
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 075e8fa..fee1e82 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -7,6 +7,26 @@
#endif
#include "sysemu.h"
+#if !defined(CONFIG_USER_ONLY)
+
+#include "softmmu_exec.h"
+
+#define MMUSUFFIX _mmu
+
+#define SHIFT 0
+#include "softmmu_template.h"
+
+#define SHIFT 1
+#include "softmmu_template.h"
+
+#define SHIFT 2
+#include "softmmu_template.h"
+
+#define SHIFT 3
+#include "softmmu_template.h"
+
+#endif
+
#define SIGNBIT (uint32_t)0x80000000
#define SIGNBIT64 ((uint64_t)1 << 63)
@@ -1002,7 +1022,7 @@ static void do_interrupt_v7m(CPUARMState *env)
case EXCP_BKPT:
if (semihosting_enabled) {
int nr;
- nr = lduw_code(env->regs[15]) & 0xff;
+ nr = cpu_lduw_code(env, env->regs[15]) & 0xff;
if (nr == 0xab) {
env->regs[15] += 2;
env->regs[0] = do_arm_semihosting(env);
@@ -1074,9 +1094,9 @@ void do_interrupt(CPUARMState *env)
if (semihosting_enabled) {
/* Check for semihosting interrupt. */
if (env->thumb) {
- mask = lduw_code(env->regs[15] - 2) & 0xff;
+ mask = cpu_lduw_code(env, env->regs[15] - 2) & 0xff;
} else {
- mask = ldl_code(env->regs[15] - 4) & 0xffffff;
+ mask = cpu_ldl_code(env, env->regs[15] - 4) & 0xffffff;
}
/* Only intercept calls from privileged modes, to provide some
semblance of security. */
@@ -1096,7 +1116,7 @@ void do_interrupt(CPUARMState *env)
case EXCP_BKPT:
/* See if this is a semihosting syscall. */
if (env->thumb && semihosting_enabled) {
- mask = lduw_code(env->regs[15]) & 0xff;
+ mask = cpu_lduw_code(env, env->regs[15]) & 0xff;
if (mask == 0xab
&& (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
env->regs[15] += 2;
@@ -1543,6 +1563,32 @@ int cpu_arm_handle_mmu_fault (CPUARMState *env,
target_ulong address,
return 1;
}
+/* try to fill the TLB and return an exception if error. If retaddr is
+ NULL, it means that the function was called in C code (i.e. not
+ from generated code or from helper.c) */
+void tlb_fill(CPUARMState *env, target_ulong addr, int is_write, int mmu_idx,
+ void *retaddr)
+{
+ TranslationBlock *tb;
+ unsigned long pc;
+ int ret;
+
+ ret = cpu_arm_handle_mmu_fault(env, addr, is_write, mmu_idx);
+ if (unlikely(ret)) {
+ if (retaddr) {
+ /* now we have a real cpu fault */
+ pc = (unsigned long)retaddr;
+ tb = tb_find_pc(pc);
+ if (tb) {
+ /* the PC is inside the translated code. It means that we have
+ a virtual CPU fault */
+ cpu_restore_state(tb, env, pc);
+ }
+ }
+ helper_exception(env, env->exception_index);
+ }
+}
+
target_phys_addr_t cpu_get_phys_page_debug(CPUARMState *env, target_ulong addr)
{
uint32_t phys_addr;
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
deleted file mode 100644
index f1933c3..0000000
--- a/target-arm/op_helper.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * ARM helper routines
- *
- * Copyright (c) 2005-2007 CodeSourcery, LLC
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, see <http://www.gnu.org/licenses/>.
- */
-#include "cpu.h"
-#include "dyngen-exec.h"
-#include "helper.h"
-
-#if !defined(CONFIG_USER_ONLY)
-
-#include "softmmu_exec.h"
-
-#define MMUSUFFIX _mmu
-
-#define SHIFT 0
-#include "softmmu_template.h"
-
-#define SHIFT 1
-#include "softmmu_template.h"
-
-#define SHIFT 2
-#include "softmmu_template.h"
-
-#define SHIFT 3
-#include "softmmu_template.h"
-
-/* try to fill the TLB and return an exception if error. If retaddr is
- NULL, it means that the function was called in C code (i.e. not
- from generated code or from helper.c) */
-/* XXX: fix it to restore all registers */
-void tlb_fill(CPUARMState *env1, target_ulong addr, int is_write, int mmu_idx,
- void *retaddr)
-{
- TranslationBlock *tb;
- CPUARMState *saved_env;
- unsigned long pc;
- int ret;
-
- saved_env = env;
- env = env1;
- ret = cpu_arm_handle_mmu_fault(env, addr, is_write, mmu_idx);
- if (unlikely(ret)) {
- if (retaddr) {
- /* now we have a real cpu fault */
- pc = (unsigned long)retaddr;
- tb = tb_find_pc(pc);
- if (tb) {
- /* the PC is inside the translated code. It means that we have
- a virtual CPU fault */
- cpu_restore_state(tb, env, pc);
- }
- }
- helper_exception(env, env->exception_index);
- }
- env = saved_env;
-}
-#endif
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 643a573..207c5d8 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -6705,7 +6705,7 @@ static void disas_arm_insn(CPUARMState * env,
DisasContext *s)
TCGv addr;
TCGv_i64 tmp64;
- insn = ldl_code(s->pc);
+ insn = cpu_ldl_code(env, s->pc);
s->pc += 4;
/* M variants do not implement ARM mode. */
@@ -8133,7 +8133,7 @@ static int disas_thumb2_insn(CPUARMState *env,
DisasContext *s, uint16_t insn_hw
/* Fall through to 32-bit decode. */
}
- insn = lduw_code(s->pc);
+ insn = cpu_lduw_code(env, s->pc);
s->pc += 2;
insn |= (uint32_t)insn_hw1 << 16;
@@ -9163,7 +9163,7 @@ static void disas_thumb_insn(CPUARMState *env,
DisasContext *s)
}
}
- insn = lduw_code(s->pc);
+ insn = cpu_lduw_code(env, s->pc);
s->pc += 2;
switch (insn >> 12) {
--
1.7.9
0006-arm-move-load-and-store-helpers-switch-to-AREG0-free.patch
Description: Text document
- [Qemu-devel] [PATCH 6/6] arm: move load and store helpers, switch to AREG0 free mode,
Blue Swirl <=