Re: [Qemu-devel] [PATCH RFC v4 08/20] target-arm: Store cp15 c0_c1 and c0_c2 in ARMCPUClass

[Alexey Starikovskiy]

On Thu, Mar 15, 2012 at 11:20 PM, Peter Maydell
<address@hidden> wrote:
> On 15 March 2012 19:08, Paul Brook <address@hidden> wrote:
>>> For now set them in the reset function.
>>
>>> +    /* TODO Move these into arm_cpu_initfn() once no longer zeroed above.*/
>>> +    memcpy(env->cp15.c0_c1, klass->cp15.c0_c1, 8 * sizeof(uint32_t));
>>> +    memcpy(env->cp15.c0_c2, klass->cp15.c0_c2, 8 * sizeof(uint32_t)); +
>>
>> Why bother copying them into the CPU state?  These are readonly, so anything
>> that needs them should be able to use the value straight from the class
>> definitions.
>
> In my (hugely delayed) cp15 rework attempt these probably go away anyway
> in favour of having each CPU register a pile of registers along the lines of
>
>    { .name = "ID_PFR0", .cp = 15, .crn = 0, .crm = 1, .opc1 = 0, .opc2 = 0,
>      .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0x00001231 },
>    { .name = "ID_PFR1", .cp = 15, .crn = 0, .crm = 1, .opc1 = 0, .opc2 = 1,
>      .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0x00000011 },
> etc.
>
> I'm not sure there's any need to retain the CPUState (or equivalent) fields
> for them at that point.
>
> -- PMM
>
Peter, with the reserved bits in most registers it might make sense to
have resetvalue in two
masks -- ones and zeros, so that you can prevent changing of those bits.

Alex.