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[Qemu-devel] [PATCH 101/111] m68k: correctly load signed word into float
From: |
Bryce Lanham |
Subject: |
[Qemu-devel] [PATCH 101/111] m68k: correctly load signed word into floating point register |
Date: |
Wed, 17 Aug 2011 15:54:06 -0500 |
From: Laurent Vivier <address@hidden>
Signed-off-by: Laurent Vivier <address@hidden>
---
target-m68k/translate.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 0a14597..987bd84 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -839,7 +839,7 @@ static inline void gen_load_FP0(DisasContext * s, int
opsize, TCGv addr)
gen_helper_exts32_FP0(cpu_env);
break;
case OS_WORD:
- tcg_gen_qemu_ld16u(QREG_FP0H, addr, index);
+ tcg_gen_qemu_ld16s(QREG_FP0H, addr, index);
gen_helper_exts32_FP0(cpu_env);
break;
case OS_LONG:
--
1.7.2.3
- [Qemu-devel] [PATCH 100/111] m68k: use log10l() to compute log10_FP0(), Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 104/111] m68k: add fsincos instruction, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 106/111] m68k: add ftanh instruction, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 111/111] m68k: move from sr can use effective addresse on m68k, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 109/111] m68k: first draft of q800 emulation (not working), Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 107/111] m68k: add flognp1 instruction, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 108/111] m68k: add fatanh instruction, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 102/111] m68k: add fcosh instruction, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 110/111] m68k: add movec instruction, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 103/111] m68k: add fasin instruction, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 101/111] m68k: correctly load signed word into floating point register,
Bryce Lanham <=
- [Qemu-devel] [PATCH 105/111] m68k: add fsinh instruction, Bryce Lanham, 2011/08/17