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[Qemu-devel] [PATCH 15/26] target-xtensa: implement CACHE group
From: |
Max Filippov |
Subject: |
[Qemu-devel] [PATCH 15/26] target-xtensa: implement CACHE group |
Date: |
Wed, 18 May 2011 02:32:41 +0400 |
All operations in this group are no-ops, because cache ought to be
transparent to applications. However cache may be abused, then we'll
need to actually implement these opcodes.
Signed-off-by: Max Filippov <address@hidden>
---
target-xtensa/translate.c | 95 ++++++++++++++++++++++++++++++++++++++++++++-
1 files changed, 94 insertions(+), 1 deletions(-)
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index 3a58444..d3509b3 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -1003,7 +1003,100 @@ static void disas_xtensa_insn(DisasContext *dc)
break;
case 7: /*CACHEc*/
- TBD();
+ if (RRI8_T < 8) {
+ HAS_OPTION(XTENSA_OPTION_DCACHE);
+ }
+
+ switch (RRI8_T) {
+ case 0: /*DPFRc*/
+ break;
+
+ case 1: /*DPFWc*/
+ break;
+
+ case 2: /*DPFROc*/
+ break;
+
+ case 3: /*DPFWOc*/
+ break;
+
+ case 4: /*DHWBc*/
+ break;
+
+ case 5: /*DHWBIc*/
+ break;
+
+ case 6: /*DHIc*/
+ break;
+
+ case 7: /*DIIc*/
+ break;
+
+ case 8: /*DCEc*/
+ switch (_OP1) {
+ case 0: /*DPFLl*/
+ HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
+ break;
+
+ case 2: /*DHUl*/
+ HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
+ break;
+
+ case 3: /*DIUl*/
+ HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
+ break;
+
+ case 4: /*DIWBc*/
+ HAS_OPTION(XTENSA_OPTION_DCACHE);
+ break;
+
+ case 5: /*DIWBIc*/
+ HAS_OPTION(XTENSA_OPTION_DCACHE);
+ break;
+
+ default: /*reserved*/
+ RESERVED();
+ break;
+
+ }
+ break;
+
+ case 12: /*IPFc*/
+ HAS_OPTION(XTENSA_OPTION_ICACHE);
+ break;
+
+ case 13: /*ICEc*/
+ switch (_OP1) {
+ case 0: /*IPFLl*/
+ HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
+ break;
+
+ case 2: /*IHUl*/
+ HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
+ break;
+
+ case 3: /*IIUl*/
+ HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
+ break;
+
+ default: /*reserved*/
+ RESERVED();
+ break;
+ }
+ break;
+
+ case 14: /*IHIc*/
+ HAS_OPTION(XTENSA_OPTION_ICACHE);
+ break;
+
+ case 15: /*IIIc*/
+ HAS_OPTION(XTENSA_OPTION_ICACHE);
+ break;
+
+ default: /*reserved*/
+ RESERVED();
+ break;
+ }
break;
case 9: /*L16SI*/
--
1.7.3.4
- [Qemu-devel] [PATCH 09/26] target-xtensa: add special and user registers, (continued)
- [Qemu-devel] [PATCH 10/26] target-xtensa: implement RST3 group, Max Filippov, 2011/05/17
- [Qemu-devel] [PATCH 11/26] target-xtensa: implement shifts (ST1 and RST1 groups), Max Filippov, 2011/05/17
- [Qemu-devel] [PATCH 12/26] target-xtensa: implement LSAI group, Max Filippov, 2011/05/17
- [Qemu-devel] [PATCH 13/26] target-xtensa: mark reserved and TBD opcodes, Max Filippov, 2011/05/17
- [Qemu-devel] [PATCH 14/26] target-xtensa: implement SYNC group, Max Filippov, 2011/05/17
- [Qemu-devel] [PATCH 15/26] target-xtensa: implement CACHE group,
Max Filippov <=
- [Qemu-devel] [PATCH 16/26] target-xtensa: implement exceptions, Max Filippov, 2011/05/17
- [Qemu-devel] [PATCH 17/26] target-xtensa: implement RST2 group (32 bit mul/div/rem), Max Filippov, 2011/05/17
- [Qemu-devel] [PATCH 18/26] target-xtensa: implement windowed registers, Max Filippov, 2011/05/17
- [Qemu-devel] [PATCH 19/26] target-xtensa: implement loop option, Max Filippov, 2011/05/17
[Qemu-devel] [PATCH 20/26] target-xtensa: implement extended L32R, Max Filippov, 2011/05/17