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[Qemu-devel] [PATCH][MIPS] FPU support for MIPS
From: |
Marius Groeger |
Subject: |
[Qemu-devel] [PATCH][MIPS] FPU support for MIPS |
Date: |
Thu, 8 Jun 2006 15:48:40 +0200 (CEST) |
Hello,
Here's another update of my previous FPU patches which brings a lot of
good stuff:
- completely switched to using the IEEE softfloat library with
it's extended support for exception/status handling
- fixed FP register implementation which tended to screw up
upon some internal offset calculation (FPR() macro)
- FP registers should behave identical on big/little endian hosts
(one of Fabrices requests)
- complete rewrite of conditional calculation
(triggerd by previous brokeness and Fabrice :-)
- implement CP1 FPR0 implementation register
- properly issue "CP1 not available" exceptions (needed badly for
Linux's lazy context switching)
- implement new insns:
cvt.w.s
cvt.w.d
floor.w.s
floor.w.d
ceil.w.s
ceil.w.d
- And my favorite: QEMU MIPS Linux now passes the "paranoia" testsuite:
No failures, defects nor flaws have been discovered.
Rounding appears to conform to the proposed IEEE standard P754.
The arithmetic diagnosed appears to be Excellent!
END OF TEST.
Regards,
Marius
--
Marius Groeger <address@hidden>
SYSGO AG Embedded and Real-Time Software
Voice: +49 6136 9948 0 FAX: +49 6136 9948 10
www.sysgo.com | www.elinos.com | www.osek.de | www.pikeos.com
qemu-mips-fpu.patch
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